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US 11,380,382 B2Granted
Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
AssigneeMicron Technology, Inc.
InventorsYu Zhang, Liang Li, Jun Wu
Life of this patent
Estimating the term…
Abstract
Embodiments of the disclosure are drawn to apparatuses, systems, and methods for providing refresh logic, such as row hammer refresh circuitry, in a location on a memory die apart from a bank logic region of the memory die. In some examples, at least some of the components of the row hammer refresh circuitry may be shared between banks of the memory.
Claims20
An apparatus comprising:
- a plurality of memory banks;
- a bank logic region located centrally to the plurality of memory banks;
- a second region separate from the bank logic region;
- an aggressor detector circuit located in the second region, wherein the aggressor detector circuit is configured to generate a match address corresponding to an aggressor row;
- and
- a refresh address generator located in the bank logic region, wherein the refresh address generator is configured to generate a refresh address based, at least in part, on the match address.
3 more elements
A method comprising:
- monitoring row access operations for a plurality of memory banks with a corresponding plurality of aggressor detector circuits;
- generating, with the plurality of aggressor detector circuits, a plurality of match addresses, each of the plurality of match addresses corresponding to one of the plurality of memory banks;
- responsive to an all-bank targeted refresh command, providing the plurality of match addresses from the aggressor detector circuits to a multiplexer;
- and
- outputting individual ones of the plurality of match addresses from the multiplexer in a time-staggered manner.
2 more elements
A memory device comprising:
- a plurality of memory banks;
- and
- a refresh control circuit comprising refresh circuitry components located in a bank logic region located central to the plurality of memory banks and row hammer refresh (RHR) circuitry components located in a second region separate from the bank logic region.
Dependencies are inferred from the claim text.