Techniques and devices for canceling memory cell variations
AssigneeMicron Technology, Inc.
InventorsYasuko Hattori, Mahdi Jamali
Life of this patent
Estimating the term…
Abstract
A memory device may include a digit line, a ferroelectric memory cell coupled with the digit line, a first capacitor including a first node and a second node, the first node coupled with the digit line using a first path and the second node coupled with the digit line using a second path different from the first path, and a switching component positioned in the second path and coupled with the second node of the first capacitor and the digit line, the switching component configured to selectively couple the second node of the first capacitor with the digit line. In some cases, the memory device may further include a second capacitor coupled with the digit line and the second node of the first capacitor.
Claims19
An apparatus comprising:
- a memory cell;
- a sense component coupled with the memory cell and configured to determine a value stored by the memory cell;
- and
- a circuit coupled with the memory cell and configured to cancel out cell-specific variations in an output signal of the memory cell during a read operation, the circuit comprising:
- a capacitor configured to affect cell-specific variation in the output signal;
- and
- a first switching component comprising a first node coupled with the first node of the capacitor and comprising a second node coupled with a digit line of the memory cell, the first switching component configured to selectively couple the first node of the capacitor with the digit line of the memory cell during portions of the read operation;
- and
- a second switching component comprising a first node coupled with the second node of the first switching component and comprising a second node coupled with a second node of the capacitor, the second switching component configured to selectively couple the second node of the capacitor with the digit line.
A method, comprising:
- coupling, using a switching component, a first node of a capacitor with a digit line of a memory cell, the switching component and the capacitor included in a circuit configured to cancel out cell-specific variations in an output signal of the memory cell during a read operation;
- coupling the first node of the capacitor with a voltage source based at least in part on coupling the first node of the capacitor with the digit line;
- coupling, for a first duration, the digit line with the memory cell based at least in part on coupling the first node of the capacitor with the voltage source;
- isolating the first node of the capacitor from the voltage source for a second duration that at least partially overlaps with the first duration;
- isolating, for a third duration, the digit line from the memory cell and the first node of the capacitor based at least in part on isolating the first node of the capacitor from the voltage source;
- and
- coupling the digit line with a second node of the capacitor for a fourth duration that at least partially overlaps with the third duration.
An apparatus, comprising:
- a memory cell;
- a circuit comprising a switching component and a capacitor, the circuit configured to cancel out cell-specific variations in an output signal of the memory cell during a read operation;
- and
- a controller coupled with the circuit and operable to cause the apparatus to:
- couple, using the switching component, a first node of the capacitor with a digit line of the memory cell;
- couple the first node of the capacitor with a voltage source based at least in part on coupling the first node of the capacitor with the digit line;
- couple, for a first duration, the digit line with the memory cell based at least in part on coupling the first node of the capacitor with the voltage source;
- isolate the first node of the capacitor from the voltage source for a second duration that at least partially overlaps with the first duration;
- isolate, for a third duration, the digit line from the memory cell and the first node of the capacitor based at least in part on isolating the first node of the capacitor from the voltage source;
- and
- couple the digit line with a second node of the capacitor for a fourth duration that at least partially overlaps with the third duration.
Dependencies are inferred from the claim text.