Clock driver and memory device comprising the same

A memory device, comprising:

• a plurality groups of memory chips;
• and
• a clock driver, wherein the clock driver comprises:
• a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol by determining toggling of the plurality pairs of input clock signals;
• a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signals;
• and
• a plurality of multiplexers coupled to the clock detector and to the PLL module, wherein each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive one group of the plurality groups of memory chips.

A method for clocking a memory device, wherein the method comprises:

• receiving a plurality pairs of input clock signals of a predetermined clocking protocol;
• generating a protocol identifier indicative of the predetermined clocking protocol by determining toggling of the plurality pairs of input clock signals;
• and
• selectively outputting, according to the protocol identifier, the plurality pairs of input clock signals or a plurality of reference clock signals generated according to at least one pair of input clock signals.