Apparatuses and methods to perform low latency access of a memory
AssigneeMicron Technology, Inc.
InventorsYuan He, Daigo Toyama
Life of this patent
Estimating the term…
Abstract
An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.
Claims23
An apparatus comprising:
- a memory array comprising a plurality of memory cells, wherein a particular one of the plurality of memory cells is configured to retain stored data based on a respective row and column address;
- a register circuit configured to store addresses and corresponding data;
- and
- a control circuit configured to receive, via a command and address bus, command and address information, wherein the command and address information includes the respective row and column address corresponding to the particular one of the plurality of memory cells of the memory array, wherein the control circuit is configured to selectively direct the command and address information including the respective row and column address to the memory array in response to a low latency mode being disabled and to direct the command and address information including the respective row and column address to the register circuit in response to the low latency mode being enabled.
A memory comprising:
- a memory array;
- a register circuit configured to store addresses and corresponding data;
- and
- a control circuit configured to receive command and address data having a respective row and column address corresponding to a particular one of a plurality of memory cells of the memory array, wherein, in a first mode of operation, cause address and data to be stored at or retrieved from the register circuit based on the command and address data corresponding to the particular one of the plurality of memory cells of the memory array, wherein, in a second mode of operation, the control circuit is configured to cause data to be stored at or retrieved from the particular one of the plurality of memory cells of the memory array based on the same command and address data.
A method comprising:
- receiving command and address information at a memory;
- directing execution of the command and address information to a low latency register circuit of the memory in response to a low latency enable bit of the command and address information indicating a first mode of operation;
- and
- directing execution of the command and address information to the memory array of the memory in response to the low latency enable bit of the command and address information indicating a second mode of operation;
- and
- in response to the command and address information including a write command:
- causing corresponding write data to be written to an available slot of the low latency register circuit when in the first mode of operation;
- and
- causing corresponding write data to be written to the memory array when the register circuit is full.
A dynamic random access memory, comprising:
- a memory array comprising a plurality of volatile memory cells each configured to store corresponding data when a corresponding one of the plurality of volatile memory cells is selected responsive to a corresponding row address and a corresponding column address;
- a register circuit configured to store data and row and column addresses corresponding to the data which have been provided externally;
- and
- a control circuit configured to receive commands and row and column addresses via a command and address bus and direct the command and row and column addresses to the register circuit, wherein, in response to the commands including a write command, the control circuit is configured to direct write data to be written to the memory array when the register circuit is full.
Dependencies are inferred from the claim text.