Semiconductor device including memory cells and method for manufacturing thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Li Chiang, Yu-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.
Claims20
A method of manufacturing a semiconductor device, comprising:
- forming logic circuitry including transistors over a substrate;
- forming first and second wiring layers over the transistors, each of the first and second wiring layers including metal wirings and an interlayer dielectric layer;
- forming a first memory array layer over the second wiring layer;
- forming a third wiring layer;
- forming a second memory array layer over the first memory array layer;
- and
- forming a fourth wiring layer, wherein:
- the first memory array layer is disposed at a same layer as the third wiring layer, and the second memory array layer is disposed at a same layer as the fourth wiring layer,
- the semiconductor device includes a logic circuit region and a memory region in plan view, and
- in the forming the first memory array layer, a first blanket memory layer including a plurality of first word lines and first bit lines is formed over the logic circuit region and the memory region, and a part of the first blanket memory layer on the logic circuit region is removed, wherein a part of the plurality of first word lines and first bit lines included in the part of the first blanket memory layer is removed when removing the part of the first blanket memory layer.
A method of manufacturing a semiconductor device including memory arrays, the method comprising:
- forming an etch stop layer over a lower metal wiring layer;
- forming a memory array layer including:
- forming a stacked structure including a first conductive layer over the etch stop layer, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, a second insulating layer over the second conductive layer, a third insulating layer over the second insulating layer, and a fourth insulating layer over the third insulating layer;
- forming bit-line patterns by patterning the stacked structure;
- forming a dielectric layer over the bit-line patterns;
- patterning the dielectric layer, thereby forming wall patterns crossing the bit-line patterns;
- forming a memory layer;
- and
- forming word line patterns by forming a third conductive layer filling spaces between the bit-line patterns and the wall patterns;
- removing a part of the memory array layer;
- and
- forming a metal wiring layer over the lower metal wiring layer.
A method of manufacturing a semiconductor device including memory arrays, the method comprising:
- forming an etch stop layer over a lower metal wiring layer;
- forming a memory array layer including:
- forming a stacked structure including a first conductive layer over the etch stop layer, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, a second insulating layer over the second conductive layer, a third insulating layer over the second insulating layer, and a fourth insulating layer over the third insulating layer;
- forming bit-line patterns by patterning the stacked structure;
- forming a dielectric layer over the bit-line patterns;
- patterning the dielectric layer, thereby forming wall patterns crossing the bit-line patterns;
- forming a memory layer;
- forming a selector material layer;
- forming a third conductive layer filling spaces between the bit-line patterns and the wall patterns;
- forming recesses along the wall patterns;
- and
- forming word line patterns by filling the recesses with a fourth conductive layer;
- removing a part of the memory array layer;
- and
- forming a metal wiring layer over the lower metal wiring layer.
Dependencies are inferred from the claim text.