Chips and electronics devices
AssigneeChangxin Memory Technologies, Inc.
InventorsKangLing Ji, Hongwen Li, Kai Tian
Life of this patent
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AssigneeChangxin Memory Technologies, Inc.
InventorsKangLing Ji, Hongwen Li, Kai Tian
Estimating the term…
The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.
A chip comprising:
A chip comprising:
Dependencies are inferred from the claim text.