Shift register having two output signals with phase lagging and driving method thereof, scan driving circuit, display panel and display device

A scan driving circuit, comprising:

• shift registers, arranged in a cascaded manner, wherein each of the shift registers includes:
• an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal;
• a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal;
• a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal;
• a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node;
• a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node;
• and
• a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, wherein:
• a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module, and
• the stabilization module includes:
• a first transistor, wherein a first terminal of the first transistor is electrically connected to the first voltage terminal, a second terminal of the first transistor is electrically connected to the first output terminal, and a control terminal of the first transistor is electrically connected to the second node;
• a second transistor, wherein a first terminal of the second transistor is electrically connected to the first voltage terminal, a second terminal of the second transistor is electrically connected to the second output terminal, and a control terminal of the second transistor is electrically connected to the second node;
• and
• a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first voltage terminal, and a second plate of the first capacitor is electrically connected to the second node,
• the first output module includes:
• a third transistor, wherein a first terminal of the third transistor is electrically connected to the first output terminal, and a second terminal of the third transistor is electrically connected to the second clock signal terminal;
• and
• a second capacitor, wherein a first plate of the second capacitor is electrically connected to the first output terminal, and a second plate of the second capacitor is electrically connected to a control terminal of the third transistor;
• and
• the second output module includes:
• a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to the second output terminal, and a second terminal of the fourth transistor is electrically connected to the third clock signal terminal;
• and
• a third capacitor, wherein a first plate of the third capacitor is electrically connected to the second output terminal, and a second plate of the third capacitor is electrically connected to a control terminal of the fourth transistor, and
• a capacitance of the third capacitor is greater than a capacitance of the second capacitor;
• an initial signal line;
• a first clock signal line;
• a second clock signal line;
• and
• a third clock signal line, wherein:
• the signal input terminal of a first-stage shift register is electrically connected to the initial signal line;
• except for the first-stage shift register, the signal input terminal of each stage shift register is electrically connected to one of the second output terminal and the first output terminal of a previous stage shift register;
• for a 3n-th stage shift register, a first clock signal terminal thereof is electrically connected to the first clock signal line, a second clock signal terminal thereof is electrically connected to the second clock signal line, and a third clock signal terminal thereof is electrically connected to the third clock signal line;
• for a 3n+1st stage shift register, a first clock signal terminal thereof is electrically connected to the third clock signal line, a second clock signal terminal thereof is electrically connected to the first clock signal line, and a third clock signal terminal thereof is electrically connected to the second clock signal line;
• for a 3n+2nd stage shift register, a first clock signal terminal thereof is electrically connected to the second clock signal line, a second clock signal terminal thereof is electrically connected to the third clock signal line, and a third clock signal terminal thereof is electrically connected to the first clock signal line;
• and
• pulses of the first clock signal line, the second clock signal line, and the third clock signal line do not overlap with each other, and are arranged sequentially in time, wherein:
• n is 0 or a positive integer.

A display panel, comprising:

• a scan driving circuit, wherein the scan driving circuit includes:
• shift registers, arranged in a cascaded manner, wherein each of the shift registers includes:
• an input module, electrically connected to a signal input terminal and a first clock signal terminal, and configured to provide a signal of the signal input terminal to a first node in response to a signal of the first clock signal terminal;
• a control module, electrically connected to a first voltage terminal, a second clock signal terminal, and a second node, and configured to provide a voltage of the first voltage terminal to the first node in response to a voltage of the second node and a signal of the second clock signal terminal;
• a reset module, electrically connected to a second voltage terminal and the first clock signal terminal, and configured to provide a voltage of the second voltage terminal to the second node in response to the signal of the first clock signal terminal;
• a first output module, electrically connected to the first node and the second clock signal terminal, and configured to provide the signal of the second clock signal terminal to a first output terminal in response to the voltage of the first node;
• a second output module, electrically connected to the first node and a third clock signal terminal, and configured to provide a signal of the third clock signal terminal to a second output terminal in response to the voltage of the first node;
• and
• a stabilization module, electrically connected to the second node and the first voltage terminal, and configured to provide the voltage of the first voltage terminal to the first output terminal and the second output terminal respectively in response to the voltage of the second node, wherein:
• a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module, and
• the stabilization module includes:
• a first transistor, wherein a first terminal of the first transistor is electrically connected to the first voltage terminal, a second terminal of the first transistor is electrically connected to the first output terminal, and a control terminal of the first transistor is electrically connected to the second node;
• a second transistor, wherein a first terminal of the second transistor is electrically connected to the first voltage terminal, a second terminal of the second transistor is electrically connected to the second output terminal, and a control terminal of the second transistor is electrically connected to the second node;
• and
• a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first voltage terminal, and a second plate of the first capacitor is electrically connected to the second node,
• the first output module includes:
• a third transistor, wherein a first terminal of the third transistor is electrically connected to the first output terminal, and a second terminal of the third transistor is electrically connected to the second clock signal terminal;
• and
• a second capacitor, wherein a first plate of the second capacitor is electrically connected to the first output terminal, and a second plate of the second capacitor is electrically connected to a control terminal of the third transistor;
• and
• the second output module includes:
• a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to the second output terminal, and a second terminal of the fourth transistor is electrically connected to the third clock signal terminal;
• and
• a third capacitor, wherein a first plate of the third capacitor is electrically connected to the second output terminal, and a second plate of the third capacitor is electrically connected to a control terminal of the fourth transistor, and
• a capacitance of the third capacitor is greater than a capacitance of the second capacitor;
• an initial signal line;
• a first clock signal line;
• a second clock signal line;
• and
• a third clock signal line, wherein:
• the signal input terminal of a first-stage shift register is electrically connected to the initial signal line;
• except for the first-stage shift register, the signal input terminal of each stage shift register is electrically connected to one of the second output terminal and the first output terminal of a previous stage shift register;
• for a 3n-th stage shift register, a first clock signal terminal thereof is electrically connected to the first clock signal line, a second clock signal terminal thereof is electrically connected to the second clock signal line, and a third clock signal terminal thereof is electrically connected to the third clock signal line;
• for a 3n+1st stage shift register, a first clock signal terminal thereof is electrically connected to the third clock signal line, a second clock signal terminal thereof is electrically connected to the first clock signal line, and a third clock signal terminal thereof is electrically connected to the second clock signal line;
• for a 3n+2nd stage shift register, a first clock signal terminal thereof is electrically connected to the second clock signal line, a second clock signal terminal thereof is electrically connected to the third clock signal line, and a third clock signal terminal thereof is electrically connected to the first clock signal line;
• and
• pulses of the first clock signal line, the second clock signal line, and the third clock signal line do not overlap with each other, and are arranged sequentially in time, wherein:
• n is 0 or a positive integer;
• a plurality of scan signal lines;
• and
• a plurality of pixel driving circuits, wherein:
• the first output terminal and the second output terminal of the shift registers of the scan driving circuit are electrically connected to the plurality of scan signal lines;
• and
• the plurality of scan signal lines is electrically connected to the plurality of pixel driving circuits.