Pixel array substrate with narrow peripheral area and narrow bezel design of display panel

A pixel array substrate, comprising:

• a substrate having a display area;
• a plurality of first signal lines, arranged on the substrate and defining a first row region and a second row region of the display area;
• a plurality of second signal lines, intersected with the first signal lines;
• a plurality of pixels, electrically connected to the corresponding first signal lines and the corresponding second signal lines respectively, wherein the pixels are arranged into a first pixel row and a second pixel row, and the first pixel row and the second pixel row are respectively disposed in the first row region and the second row region;
• a first demultiplexer, disposed in the first row region and electrically connected to a part of the second signal lines;
• a second demultiplexer, disposed in the second row region and electrically connected to another part of the second signal lines;
• and
• a first connecting line and a second connecting line, electrically connected to the first demultiplexer and the second demultiplexer respectively, wherein an electrical resistivity of the first connecting line and the second connecting line is greater than an electrical resistivity of the first signal lines and the second signal lines,
• the first connecting line and the second connecting line respectively have at least one first part and at least one second part, wherein the first part has a first width in an extension direction perpendicular to the first signal lines, the second part has a second width in an extension direction perpendicular to the second signal lines, and the first width is not equal to the second width.