Enhanced techniques for traversing ray tracing acceleration structures

A ray tracing acceleration hardware device, comprising:

• memory configured to store at least portions of an acceleration data structure;
• ray storage configured to store an opcode from a ray received from a processor;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified by the opcode if a flag is in a first state, and (b) ignoring the operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor, wherein the flag is in a complet including the node and one or more child nodes of the node, and wherein the node includes a node parameter that is used in the logical operation with one or more parameters from the ray.

A ray tracing acceleration hardware device, comprising:

• memory configured to store at least portions of an acceleration data structure;
• ray storage configured to store an opcode from a ray received from a processor;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified by the opcode if a flag is in a first state, and (b) ignoring the operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor, wherein the node is in a bottom level acceleration structure (BLAS) complet, and wherein the traversal circuitry is further configured to, if the flag is not set, to perform the logical operation according to the opcode at each child node of the node.

A ray tracing acceleration hardware device, comprising:

• memory configured to store at least portions of an acceleration data structure;
• ray storage configured to store an opcode from a ray received from a processor;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified by the opcode if a flag is in a first state, and (b) ignoring the operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor, wherein the flag is set in the node, and wherein the traversal circuitry is further configured to, if the flag is in the second state, determining, based on an invert bit in a child node of the node, whether or not to traverse the child node without performing the operation on the child node.

A ray tracing system comprising:

• a processor configured to generate a ray including an opcode;
• and
• a ray tracing acceleration hardware device, comprising:
• memory configured to store at least portions of an acceleration data structure;
• ray storage configured to store the opcode from the ray;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing, using the opcode, at least one parameter specified in the ray other than the opcode, and at least one parameter specified in a child node of the node, an operation specified in the opcode if a flag included in the node is in a first state, and (b) ignoring the operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.

A ray tracing acceleration method, comprising:

• receiving, in a hardware coprocessor, a ray from a processor, the ray specifying an opcode;
• storing the opcode in a ray storage in the hardware coprocessor;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing, using the opcode, at least one parameter specified in the ray other than the opcode, and at least one parameter specified in a child node of the node, an operation specified in the opcode if a flag included in the node is in a first state, and (b) ignoring the logical operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor.

A ray tracing hardware acceleration method, comprising:

• receiving ray indicia including indicia defining an operation;
• receiving first acceleration data structure node indicia for a first node, the received first acceleration data structure node indicia comprising a first indicator;
• testing the received ray indicia for intersection against the first node including performing the operation against the first node in response to the first indicator, wherein the testing is performed using the indicia defining the operation, at least one other indicia specified in the ray indicia, and at least one indicia specified in a child node of the first node;
• receiving acceleration data structure node indicia for a second node, the received second acceleration data structure node indicia comprising a second indicator;
• and
• testing the received ray indicia for intersection against the second node but not performing the operation against the second node in response to the second indicator.

A ray tracing acceleration method, comprising:

• receiving, in a hardware coprocessor, a ray from a processor, the ray specifying an opcode;
• storing the opcode in a ray storage in the hardware coprocessor;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified in the opcode if a flag is in a first state, and (b) ignoring the logical operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor,
• wherein the flag is in a complet including the node and one or more child nodes of the node, and wherein the node includes a node parameter that is used in the logical operation with one or more parameters from the ray.

A ray tracing acceleration method, comprising:

• receiving, in a hardware coprocessor, a ray from a processor, the ray specifying an opcode;
• storing the opcode in a ray storage in the hardware coprocessor;
• traversal circuitry configured to traverse the acceleration data structure according to the ray, the traversing including, at a node of the acceleration data structure, (a) performing an operation specified in the opcode if a flag is in a first state, and (b) ignoring the logical operation if the flag is in a second state;
• and
• intersection detection circuitry configured to detect one or more intersections of the ray with one or more nodes of the acceleration structure during the traversing and return information of the detected intersection to the processor,
• wherein the node is in a bottom level acceleration structure (BLAS) complet, and wherein the traversal circuitry is further configured to, if the flag is not set, to perform the logical operation according to the opcode at each child node of the node.