Architecture of in-memory computing memory device for use in artificial neuron

An in-memory computing memory device applied in an artificial neuron, comprising:

• an array of memory cells arranged in rows and columns and vertically divided into (M+1) lanes;
• a plurality of first word lines arranged corresponding to the respective memory cell rows, each connected to the memory cells in a corresponding row;
• a plurality of first bit lines arranged corresponding to the respective memory cell columns, each connected to the memory cells in a corresponding column;
• (M+1) input circuits having (M+1) data input terminals and coupled to the first bit lines, wherein each lane comprises P memory cell columns and a corresponding input circuit, P memory cells in each row for each lane storing a weight value Wi, wherein the input circuit in each lane charges a predefined first bit line with a default amount of charge proportional to an input synapse value Xi at its data input terminal and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current;
• a first wordline driver to activate one of the first word lines to retain a final amount of charge in each first bit line that is equivalent to a first product of its distributed amount of charge and a bit value stored in its corresponding memory cell;
• and
• an evaluation circuitry to selectively couple a selected number of the first bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values at the (M+1) data input terminals and the activated first word line;
• wherein the average voltage is associated with the accumulation of the final amount of charge in each selected first bit line.