Advanced cell-aware fault model for yield analysis and physical failure analysis

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• identify one or more transistor characteristics within a netlist associated with a semiconductor chip design;
• execute an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of a cell of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design and wherein providing the inputs to input pins of the cell causes the cell to generate results at one or more output pins of the cell;
• correlate one or more faults detected with one or more transistor characteristics within the netlist based at least in part on the results of the one or more fault test models to identify one or more faulty transistors within the semiconductor chip design;
• and
• provide a user interface identifying the one or more faulty transistors within the semiconductor chip design.

A non-transitory computer readable medium comprising stored instructions, which

• when executed by a processor, cause the processor to:
• identify one or more transistor characteristics within a netlist associated with a semiconductor chip design;
• execute an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of a cell of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design and wherein providing the inputs to input pins of the cell causes the cell to generate results at one or more output pins of the cell;
• correlate one or more faults detected with one or more transistor characteristics within the netlist based at least in part on the results of the one or more fault test models to identify one or more faulty transistors within the semiconductor chip design;
• and
• provide a user interface identifying the one or more faulty transistors within the semiconductor chip design.