IC chip test engine

A system comprising:

• a non-transitory memory that stores machine-readable instructions;
• and
• a processing unit that accesses the memory and executes the machine-readable instructions, the machine-readable instructions comprising an integrated circuit (IC) chip test engine that:
• selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an intellectual property (IP) block and a test data register (TDR) logically arranged upstream from the IP block;
• identifies a set of segment insertion bits (SIBs) gating access to the selected instrument;
• selects a scan chain for operating the set of SIBs to control access to the selected instrument;
• augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state;
• and
• generates a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern of a plurality of test patterns to the IP block of the selected instrument, wherein a last load vector of the set of load vectors includes a respective test pattern of the plurality of test patterns and data to transition the furthest downstream SIB of the set of SIBs that gates access to the selected instrument to a closed state, such that the furthest downstream SIB is loaded with a command to transition to the closed state before completion of loading the respective test pattern of the last load vector in the TDR of the selected instrument.

A method for testing an integrated circuit (IC) chip implemented by an IC chip test engine executing on a computing platform, the method comprising:

• selecting a test algorithm based on architecture data characterizing a layout of an IC chip corresponding to an IC chip design and instrument access script characterizing operations executed during a test of the IC chip corresponding to the IC design;
• selecting an instrument in the IC design for testing, the selected instrument comprising an intellectual property (IP) block and a test data register (TDR) logically arranged upstream from the IP block;
• selecting a scan chain for operating a set of SIBs to control access to the selected instrument;
• augmenting the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state;
• generating a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern of a plurality of test patterns to the IP block of the selected instrument, wherein a last load vector of the set of load vectors includes a respective test pattern of the plurality of test patterns and data to transition the furthest downstream SIB of the set of SIBs that gates access to the selected instrument to a closed state, such that the furthest downstream SIB is loaded with a command to transition to the closed state before completion of loading the respective test pattern of the last load vector in the TDR of the selected instrument;
• and
• executing the scan chain to test the IC chip corresponding to the IC design.