Integrated circuit design method, system and computer program product

A system, comprising a processor configured to:

• extract a plurality of features of a plurality of paths in an integrated circuit (IC) layout diagram,
• cluster the plurality of paths into a plurality of clusters,
• for each cluster among the plurality of clusters,
• calculate a biasing of each feature among the plurality of features, and
• based on the calculated biasing of each feature among the plurality of features, determine a dominant feature for said each cluster, the dominant feature included in the plurality of features,
• based on the dominant features of the plurality of clusters, create a plurality of groups of paths from the plurality of clusters, each group among the plurality of groups having a unique dominant feature among the dominant features,
• for each group among the plurality of groups,
• perform automatic test pattern generation (ATPG) to generate at least one test pattern,
• perform a test of at least one path in said each group using the generated at least one test pattern, and
• in response to the test indicating that the at least one path fails, cause modification of at least one of
• the IC layout diagram,
• at least a portion of at least one library having cells included in the IC layout diagram, or
• a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

A computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by a processor, cause the processor to:

• create a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram, by
• clustering the plurality of paths into a plurality of clusters,
• determining a dominant feature for each cluster among the plurality of clusters, the dominant feature included in a plurality of features of the plurality of paths, the plurality of features including at least one of
• a physical dimension of at least one element in the IC layout diagram, or
• slack of the plurality of paths,
• designating each cluster having the dominant feature different from dominant features of other clusters as a group among the plurality of groups, and
• merging clusters having the same dominant feature to obtain a further group among the plurality of groups,
• perform a test of at least one path in a group among the plurality of groups;
• and
• in response to the at least one path failing the test, cause modification of at least one of:
• the IC layout diagram,
• at least a portion of at least one library having cells included in the IC layout diagram, or
• a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.