Write-back invalidate by key identifier

A system comprising:

• a memory;
• a snoop filter coupled to the memory;
• and
• a core coupled to a snoop filter, to a memory controller, and to the memory, the memory controller to secure data of multiple domains, executed by the core, according to corresponding key identifiers, wherein a first key identifier for a first domain of the multiple domains is associated with physical addresses of the memory that store data of the first domain;
• wherein, to flush and invalidate cache lines associated with the first key identifier, the core is to execute an instruction, which comprises the first key identifier, to generate a transaction comprising the first key identifier;
• and
• in response to the transaction, the snoop filter is to:
• identify matching entries of the snoop filter by a comparison of the first key identifier with at least part of an address tag of a plurality of entries in the snoop filter, the matching entries associated with cache lines stored in cache of multiple cores;
• write back, to the memory, data stored in the cache lines associated with the matching entries;
• and
• mark the matching entries of the snoop filter as invalid, wherein a key identifier cache (KIC) structure is to store the key identifiers, which are searched for matches with the first key identifier, and
• a metadata storage structure is to store address tags, which correspond to the plurality of entries in the KIC structure, and associated coherency bits.

A method comprising:

• securing, by a memory controller, data of multiple domains according to corresponding key identifiers, wherein a first key identifier for a first domain of the multiple domains is associated with physical addresses of memory that store data of the first domain;
• executing, by a processor core coupled to the memory controller, an instruction, which comprises the first key identifier, to generate a transaction comprising the first key identifier, wherein the instruction is to flush and invalidate cache lines associated with the first key identifier;
• and
• responsive to execution of the instruction and by a last level cache (LLC) coupled to the processor core:
• identifying matching entries in the LLC by comparing the first key identifier with at least part of an address tag of a plurality of entries in a tag storage structure, the matching entries associated with cache lines of the LLC;
• writing back, to the memory, data stored in the cache lines associated with the matching entries;
• and
• marking the matching entries of the tag storage structure as invalid, wherein the tag storage structure a key identifier cache (KIC) structure to store the key identifiers, which are searched for matches with the first key identifier, and
• a metadata storage structure to store address tags, which correspond to the plurality of entries in the KIC structure, and associated coherency bits.