Device and method for flexibly summing matrix values

An integrated circuit device, comprising:

• a matrix transpose component configured to transpose an initial matrix of elements to output an output matrix of the elements that have been transposed, wherein:
• each element of the initial matrix of elements is represented using a first number of bits;
• each value of a group of values stored in an input matrix corresponding to the initial matrix is represented using a second number of bits greater than the first number of bits;
• and
• each value of the group of values is stored as split segments across more than one element of the elements of the initial matrix;
• a matrix processing component configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix;
• a data alignment component configured to modify at least a portion of elements of a result of the matrix processing component;
• and
• a data reduction component configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values;
• and
• wherein the integrated circuit device is an application-specific integrated circuit.

A method, comprising:

• using a hardware matrix transpose component of an application-specific integrated circuit device to transpose an initial matrix of elements to output an output matrix of the elements that have been transposed, wherein:
• each element of the initial matrix of elements is represented using a first number of bits;
• each value of a group of values stored in an input matrix corresponding to the initial matrix is represented using a second number of bits greater than the first number of bits;
• and
• each value of the group of values is stored as split segments across more than one element of the elements of the initial matrix;
• using a hardware matrix processing component of the application-specific integrated circuit device to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the elements that have been transposed is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix;
• using a hardware data alignment component of the application-specific integrated circuit device to modify at least a portion of elements of a result of multiplying the first multiplication matrix with the second multiplication matrix;
• and
• using a hardware data reduction component of the application-specific integrated circuit device to sum at least the elements of the modified result of multiplying the first multiplication matrix with the second multiplication matrix to determine a sum of the group of values.