Arithmetic logic unit layout for a processor

A processor having a plurality of groups of arithmetic logic units (ALUs), each group including first, second and third ALUs, the processor comprising:

• each of the groups of ALUs at least partially defining a locally predefined range smaller than a range of the plurality of ALUs;
• within each group of ALUs:
• the first ALU having on a first side an input and an output;
• the second ALU having:
• a first side facing the first side of the first ALU;
• an input and an output on the first side of the second ALU being in rotated orientation relative to the input and the output of the first side of the first ALU;
• and
• an output on a second side of the second ALU, the second side of the second ALU being parallel to the first side of the second ALU;
• the third ALU having:
• a first side facing the second side of the second ALU;
• and
• an input and an output on the first side of the third ALU;
• the input of the first side of the first ALU being logically directly connected to the output of the first side of the second ALU;
• the input of the first side of the second ALU being logically directly connected to the output of the first side of the first ALU;
• and
• the output on the second side of the second ALU being logically directly connected to the input on the first side of the third ALU;
• a common pathway extending into each group between the first and second ALUs, the common pathway being a conduit by which data is provided to and received from each group of ALUs and exchanged between the groups of ALUs;
• wherein the processor has a clock speed that is too fast to guarantee execution, within a single clock cycle, of a combination of:
• (a) a most time-consuming process that could be performed by any of the first, second and/or third ALUs with one of the groups, and
• (b) receive a needed input, for performing the most time-consuming process in the one of the groups, from an ALU of the processor that is outside of the locally predefined range of the one of the groups.

A processor having a plurality of groups of arithmetic logic units (ALUs), each group including first, second and third ALUs, the processor comprising:

• within each group of ALUs:
• the first ALU having on a first side an input and an output;
• the second ALU having:
• a first side facing the first side of the first ALU;
• an input and an output on the first side of the second ALU and being in rotated orientation relative to the input and the output of the first side of the first ALU;
• and
• an output on a second side of the second ALU;
• the third ALU having:
• a first side facing the second side of the second ALU;
• and
• an input and an output on the first side of the third ALU;
• the input of the first side of the first ALU being logically directly connected to the output of the first side of the second ALU;
• the input of the first side of the second ALU being logically directly connected to the output of the first side of the first ALU;
• the output on the second side of the second ALU being logically directly connected to the input on the first side of the third ALU;
• and
• a common pathway extending into each group between the first and second ALUs, the common pathway being a conduit by which data is provided to and received from each group of ALUs and exchanged between the groups of ALUs;
• wherein the processor has a clock speed that is too fast to accommodate a combination of:
• (a) a most time consuming process that could be performed in one clock cycle by any of the first, second and/or third ALUs within a particular one of the groups of ALUs, and
• (b) receive any needed inputs from outside the particular one of the groups of ALUs.