Secondary device detection using a synchronous interface
AssigneeMicron Technology, Inc.
InventorsDean E. Walker, Tony Brewer
Life of this patent
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Abstract
A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.
Claims18
An apparatus comprising:
- a primary chiplet couplable to multiple secondary chiplets using a serial peripheral interface (SPI) interface configured for an SPI protocol, wherein the primary chiplet includes first and second data ports coupled to respective first and second data channels of the SPI interface, wherein the primary chiplet is configured to:
- send a first message using the first data port, the first message comprising a command field and a chiplet identification field, the command field configured to access a first selected chiplet of the multiple secondary chiplets, the first selected chiplet having an identifier corresponding to the chiplet identification field and the first selected chiplet configured as an SPI secondary device;
- and
- receive, using the second data port, a response message from the first selected chiplet in response to the first message, wherein the response message comprises a secondary device status field that includes information from the first selected chiplet about whether a register operation successfully completed, whether a register protocol or parity error exists, and whether a register operation was deferred.
A system comprising:
- a primary chiplet coupled to multiple secondary chiplets using a serial peripheral interface (SPI) interface configured to use an SPI protocol;
- and
- a first selected chiplet of the multiple secondary chiplets, the first selected chiplet configured to interface with the primary chiplet using the SPI interface;
- wherein the primary chiplet is configured to perform operations comprising:
- send a clock signal to the first selected chiplet using a clock channel of the SPI interface;
- send a first message using a first data channel of the SPI interface, the first message comprising a command field, a chiplet identification field, and a register address field, the command field including one or more bits to enable a controller on the first selected chiplet, and the register address field including one or more bits to address a particular memory register on the first selected chiplet, wherein the first selected chiplet is identified by information in the chiplet identification field;
- and
- receive, using a second data channel of the SPI interface, a response to the first message from the first selected chiplet, the response comprising a device status field, wherein the device status field includes information about whether a register operation successfully completed at the first selected chiplet, whether a register protocol or parity error exists at the first selected chiplet, and whether a register operation was deferred at the first selected chiplet.
A method for determining whether a secondary device is available to communicate with a primary device using a serial peripheral interface (SPI) interface configured for an SPI protocol, wherein the primary device includes a data input port and a data output port, and wherein the primary device is configured to provide a pull-up signal at the data input port, the method comprising:
- at the primary device,
- sending a clock signal using a clock port and a clock channel of the SPI interface;
- sending a first message using the data output port and a first data channel of the SPI interface, the first message comprising a command field configured to access the secondary device, a device identification field configured to identify the secondary device from other devices coupled to the first data channel of the SPI interface, a register address field configured to identify a particular register location at the secondary device, and a data message field;
- receiving signal magnitude information from the data input port over multiple sequential cycles of the clock signal;
- and
- determining an operation status of the secondary device or absence of the secondary device based on a relationship between a reference magnitude of the pull-up signal and the signal magnitude information received from the data input port over the multiple sequential cycles of the clock signal.
Dependencies are inferred from the claim text.