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US 11,379,401 B2Granted
Deferred communications over a synchronous interface
AssigneeMicron Technology, Inc.
InventorsDean E. Walker, Tony Brewer
Life of this patent
Estimating the term…
Abstract
A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.
Claims20
An apparatus comprising:
- a first chiplet couplable to multiple other chiplets using a serial peripheral interface (SPI) configured for an SPI protocol, the first chiplet configured as an SPI primary device, wherein the first chiplet is configured to:
- send a first message across the SPI interface, the first message comprising a first command field and a register address field, wherein the first message is configured to access a first register corresponding to the register address field at a first selected chiplet of the multiple other chiplets, the first selected chiplet configured as an SPI secondary device, and wherein the first command field indicates an initial request for the first selected chiplet;
- receive a response message from the first selected chiplet in response to the first message, wherein the response message comprises a secondary device status field indicating a response deferral;
- and
- in response to receiving the response message, send a second message across the SPI interface, the second message comprising a second command field that is different from the first command field and indicates a subsequent request for the first selected chiplet, wherein the second message is configured to access the first register at the first selected chiplet.
2 more elements
A system comprising:
- a first chiplet coupled to multiple other chiplets, the first chiplet configured to generate a clock signal;
- and
- a first selected chiplet of the multiple other chiplets, the first selected chiplet configured to interface with the first chiplet using a serial peripheral interface (SPI) protocol;
- wherein the first chiplet is configured to perform operations comprising:
- enable a controller on the first selected chiplet;
- send the clock signal to the first selected chiplet;
- send a first message to the first selected chiplet using the SPI interface, wherein the first message comprises a command field and a register address field, the command field including one or more bits to enable the controller to access memory registers of the first selected chiplet, and the register address field including one or more bits to address a particular memory register on the first selected chiplet;
- in response to receiving a deferral message from the first selected chiplet, send a second message to the first selected chiplet using the SPI interface, wherein the second message includes a different second command field and the second message excludes the register address field;
- and
- wherein, in response to receiving the second message, the first selected chiplet is configured to:
- send a response message to the first chiplet using the SPI interface, wherein the response message comprises a payload corresponding to the register address field in the first message.
8 more elements
A method comprising:
- at a first chiplet configured to be communicatively coupled to a second chiplet using a serial peripheral interface (SPI) interface bus,
- sending a first message to the second chiplet, wherein the first message comprises a first command field and a register address field, wherein the first message is configured to access a first register corresponding to the register address field at the second chiplet, and the first command field indicates an initial request;
- receiving a response message from the second chiplet in response to the first message from the first chiplet, the response message comprising a secondary device status field, wherein the secondary device status field includes one or more bits indicating a deferral to provide a data payload to the first chiplet;
- and
- in response to receiving the response message, sending a second message to the second chiplet, wherein the second message excludes the register address field and the second message includes a second command field that is different from the first command field, and the second message indicates a subsequent request corresponding to the register address field from the first message.
2 more elements
Dependencies are inferred from the claim text.