Route demultiplexed signal pairs
AssigneeHewlett-Packard Development Company, L.P.
InventorsMengistu Taye, Evan Lu
Life of this patent
Estimating the term…
Abstract
Example implementations relate to route demultiplexed signal pairs. In some examples, a motherboard of a computing device can include a chipset, a first Peripheral Component Interconnect Express (PCIe) bus, a second PCIe bus, a riser slot, and a demultiplexer connected to the chipset to selectively route particular signal pairs from the chipset to at least one of the first PCIe bus, the second PCIe bus, and the riser slot based on whether a riser card is connected to the riser slot.
Claims10
A motherboard of a computing device, comprising:
- a first Peripheral Component Interconnect Express (PCIe) bus;
- a second PCIe bus;
- a riser slot;
- a chipset to route:
- a first signal pair to a demultiplexer;
- a second signal pair directly to the first PCIe bus;
- a third signal pair to the demultiplexer;
- and
- a fourth signal pair directly to the second PCIe bus;
- and
- the demultiplexer connected to the chipset to selectively route, based on a riser card being connected to the riser slot:
- a first demultiplexed signal pair of the first signal pair to the riser slot;
- a first demultiplexed signal pair of the third signal pair to the riser slot;
- a second demultiplexed signal pair of the first signal pair to the first PCIe bus;
- and
- a second demultiplexed signal pair of the third signal pair to the second PCIe bus.
A motherboard of a computing device, comprising:
- a chipset to generate and route a first signal pair, a second signal pair, a third signal pair, and a fourth signal pair;
- a first Peripheral Component Interconnect Express (PCIe) bus to receive the second signal pair directly from the chipset;
- a second PCIe bus to receive the fourth signal pair directly from the chipset;
- a riser slot;
- and
- a demultiplexer connected to the chipset to selectively route, based on a riser card being connected to the riser slot:
- a first demultiplexed signal pair of the first signal pair to the riser slot;
- a first demultiplexed signal pair of the third signal pair to the riser slot;
- a second demultiplexed signal pair of the first signal pair to the first PCIe bus;
- and
- a second demultiplexed signal pair of the third signal pair to the second PCIe bus.
A method, comprising:
- generating, by a chipset of a motherboard, a first signal pair, a second signal pair, a third signal pair, and a fourth signal pair;
- routing, by the chipset:
- the first signal pair and the third signal pair to a demultiplexer;
- and
- the second signal pair directly to a first Peripheral Component Interconnect Express (PCIe) bus;
- and
- the fourth signal pair directly to a second PCIe bus;
- demultiplexing, by the demultiplexer:
- the first signal pair into a first demultiplexed signal pair and a second demultiplexed signal pair of the first signal pair;
- and
- the third signal pair into a first demultiplexed signal pair and a second demultiplexed signal pair of the third signal pair;
- selectively routing, by the demultiplexer in response to a select signal received by the demultiplexer from the riser slot indicating that a riser card is connected to the riser slot:
- the first demultiplexed signal pair of the first signal pair to the riser slot;
- the first demultiplexed signal pair of the third signal pair to the riser slot;
- the second demultiplexed signal pair of the first signal pair to the first PCIe bus;
- and
- the second demultiplexed signal pair of the third signal pair to the second PCIe bus.
Dependencies are inferred from the claim text.