Credit scheme for multi-queue memory controllers
AssigneeAdvanced Micro Devices, Inc.
InventorsKedarnath Balakrishnan, Shriram Ravichandran
Life of this patent
Estimating the term…
Abstract
A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.
Claims28
A memory controller, comprising:
- an address decoder having a first input for receiving memory access requests, a first output, and a second output;
- a first command queue having an input coupled to the first output of the address decoder for receiving memory access requests for a first memory channel, and a number of entries for holding memory access requests;
- a second command queue having an input coupled to the second output of the address decoder for receiving memory access requests for a second memory channel, and a number of entries for holding memory access requests;
- and
- a request credit control circuit coupled to the first command queue, and the second command queue, the request credit control circuit operable to track a number of outstanding request credits, and to issue a request credit based on a number of available entries of the first and second command queues.
A method, comprising:
- receiving a plurality of memory access requests at a memory controller;
- decoding addresses of the memory access requests and selecting one of a first memory channel and a second memory channel to receive each of the memory access requests;
- after decoding the addresses, sending each memory access request to one of a first command queue associated with the first memory channel and a second command queue associated with the second memory channel;
- and
- responsive to a designated event, issuing a request credit based on the number of available entries of the first and second command queues.
A data processing system, comprising:
- a data fabric;
- a first memory channel and a second memory channel;
- and
- a memory controller coupled to the data fabric and the first and second memory channels for fulfilling memory access requests received over the data fabric from at least one memory accessing engine, the memory controller comprising:
- an address decoder having a first input for receiving memory access requests, a first output, and a second output;
- a first command queue having an input coupled to the first output of the address decoder for receiving memory access requests for a first memory channel, and a number of entries for holding memory access requests;
- a second command queue having an input coupled to the second output of the address decoder for receiving memory access requests for a second memory channel, and a number of entries for holding memory access requests;
- and
- a request credit control circuit coupled to the first command queue, and the second command queue, the request credit control circuit operable to track a number of outstanding request credits, and to issue a request credit based on a number of available entries of the first and second command queues.
Dependencies are inferred from the claim text.