Main memory device having heterogeneous memories, computer system including the same, and data management method thereof
AssigneeSK hynix Inc.
InventorsMi Seon Han, Yun Jeong Mun, Young Pyo Joo
Life of this patent
Estimating the term…
Abstract
A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.
Claims34
A main memory device comprising:
- a first memory device;
- and
- a second memory device having an access latency different from that of the first memory device,
- wherein the first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region,
- wherein the at least one region includes a plurality of pages,
- wherein the first memory device manages the access count for the at least one region rather than each of the plurality of pages,
- wherein the first memory device comprises a first memory and a first controller which controls an operation of the first memory,
- wherein the first controller comprises:
- an access count storage circuit configured with an access count field in which the access count for the at least one region is stored and a hot page address field in which an address of the hot page is stored;
- and
- an access management circuit configured to increment the access count each time the at least one region is accessed, and
- wherein, when the access count for the at least one region reaches a threshold value, the access management circuit determines a last accessed page of the at least one region as the hot page, and stores the address of the hot page in the access count storage circuit.
A main memory device comprising:
- a first memory device;
- and
- a second memory device having a power consumption per unit time different from that of the first memory device,
- wherein the first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region,
- wherein the at least one region includes a plurality of pages,
- wherein the first memory device manages the access count for the at least one region rather than each of the plurality of pages, and
- wherein the first memory device comprises a first memory and a first controller which controls an operation of the first memory,
- wherein the first controller comprises:
- an access count storage circuit configured with an access count field in which the access count for the at least one region is stored and a hot page address field in which an address of the hot page is stored;
- and
- an access management circuit configured to increment the access count each time the at least one region is accessed, and
- wherein, when the access count for the at least one region reaches a threshold value, the access management circuit determines a last accessed page of the at least one region as the hot page, and stores the address of the hot page in the access count storage circuit.
A computer system comprising:
- a central processing unit (CPU);
- and
- a main memory device coupled with the CPU through a system bus,
- wherein the main memory device comprises:
- a first memory device;
- and
- a second memory device having an access latency shorter than that of the first memory device, and
- wherein the first memory device determines, based on an access count for each of one or more regions of the first memory device, a hot page included in at least one of the one or more regions,
- wherein the each of the one or more regions include a plurality of pages,
- wherein the first memory device manages the access count for the each of the one or more regions rather than each of the plurality of pages,
- wherein the first memory device comprises a first memory and a first controller which controls an operation of the first memory, and
- wherein the first controller comprises:
- an access count storage circuit configured with an access count field in which the access count for each of the one or more regions are stored and a hot page address field in which an address of the hot page is stored;
- and
- an access management circuit configured to increment, each time each of the one or more regions is accessed, the access count corresponding to the region accessed, and
- wherein, when an access count of a region of the one or more regions reaches a threshold value, the access management circuit determines a last accessed page in the corresponding region as the hot page, and stores an address corresponding to the determined hot page in the access count storage circuit, as the address of the hot page.
A data management method of a computer system including a central processing unit (CPU) and a main memory device which is coupled with the CPU through a system bus and is configured with a first memory device and a second memory device having different access latencies, the data management method comprising:
- transmitting, by the CPU to the first memory device, a hot page checking command for checking whether a hot page exists in a first memory of the first memory device;
- transmitting, by the first memory device to the CPU, one of a first response including an address corresponding to the hot page in the first memory and a second response indicating that the hot page does not exist in the first memory, depending on whether the hot page exists or not;
- and
- transmitting, by the CPU to the main memory device, when the first response is received from the first memory device, a data migration command for exchanging hot data stored in the hot page of the first memory and cold data in a second memory of the second memory device,
- wherein the first memory device includes:
- at least one region having a plurality of pages;
- an access count storage circuit configured with an access count field in which the access count for each of the at least one region is stored and a hot page address field in which an address of the hot page is stored;
- and
- an access management circuit configured to increment, each time each of the at least one region is accessed, the access count corresponding to the region accessed, and
- wherein, when an access count for the at least one region reaches a threshold value, the first memory device determines a last accessed page of the at least one region as the hot page, and stores an address corresponding to the hot page in the access count storage circuit.
A memory system comprising:
- a first memory device including plural groups each having one or more first memory regions;
- a second memory device including plural second memory regions;
- a first controller configured to determine, based on an access count for each of the plural groups of the first memory device, a hot memory region included in one of the plural groups;
- and
- a second controller configured to identify a cold memory region, which is least recently accessed among the second memory regions,
- wherein the first and second controllers respectively control the first and second memory devices to swap data between the hot memory region and the cold memory region,
- wherein the first controller comprises:
- an access count storage circuit configured with an access count field in which the access count for at least one memory region of the first memory device is stored and a hot memory region address field in which an address of a hot memory region included in the at least one memory region is stored;
- and
- an access management circuit configured to increment the access count each time the at least one memory region is accessed, and
- wherein, when an access count of a group of the plural groups reaches a threshold value, the first controller determines a last accessed memory region in the corresponding group as the hot memory region, and stores an address corresponding to the determined hot memory region in the access count storage circuit.
A memory system comprising:
- a first memory device including plural groups each having one or more first memory regions;
- a second memory device;
- a first controller configured to determine, based on an access count for each of the plural groups of the first memory device, a hot memory region included in one of the plural groups;
- and
- a second controller configured to control an operation of the second memory device,
- wherein the first and second controllers respectively control the first and second memory devices to migrate data of the hot memory region to the second memory device,
- wherein the first controller comprises:
- an access count storage circuit configured with an access count field in which the access count for at least one memory region of the first memory device is stored and a hot memory region address field in which an address of a hot memory region included in the at least one memory region is stored;
- and
- an access management circuit configured to increment the access count each time the at least one memory region is accessed, and
- wherein, when an access count of a group of the plural groups reaches a threshold value, the first controller determines a last accessed memory region in the corresponding group as the hot memory region, and stores an address corresponding to the determined hot memory region in the access count storage circuit.
Dependencies are inferred from the claim text.