Differential cache block sizing for computing systems

A method for differential cache block sizing, the method, comprising:

• determining, upon a vector prefetch request at a cache, a number of available cache blocks based on a payload length corresponding to an available channel bandwidth of a main memory interface to a main memory and a cache block size for the cache, the vector prefetch request comprising a request for vector prefetch request cache blocks including a starting cache block and one or more related cache blocks that are related to the starting cache block;
• scanning, when there are available cache blocks, a missing address storage unit (MASU) accessible to the cache to determine the existence of a relationship between the vector prefetch request and any associated cache blocks associated with one or more entries in the MASU;
• generating a main memory request including indicators for the vector prefetch request cache blocks, and any associated cache blocks, wherein a sum of a number of vector prefetch request cache blocks added to a number of any associated cache blocks is equal to the determined number of available cache blocks;
• sending the main memory request to the main memory to obtain data associated with the vector prefetch request cache blocks, and any associated cache blocks;
• storing the data received for the vector prefetch request cache blocks in the cache after evicting valid data from the cache;
• and
• storing the data received for each of the associated cache blocks in the cache depending on a cache replacement algorithm that determines whether or not to store the data received for each of the associated cache blocks based on whether or not cached data identified by the cache replacement algorithm is valid.

A computing system for differential cache block sizing, comprising:

• a hierarchical memory system including multiple caches including a first cache;
• a prefetcher configured to generate and send prefetch requests towards the hierarchical memory system;
• and
• a cache control unit associated with the first cache, the cache control unit configured to:
• determine, for a missed cache block from a cache miss, one or more associated cache blocks based on a difference between an available channel bandwidth of a main memory interface to a main memory and a cache block size for the first cache;
• generate a main memory request including at least one indicator for the missed cache block and the determined one or more associated cache blocks;
• send the main memory request to the main memory to obtain data associated with the missed cache block and each of the determined one or more associated cache blocks;
• store the data received for the missed cache block in the first cache after evicting valid data from the cache;
• and
• store the data received for each of the determined one or more associated cache blocks in the first cache depending on a cache replacement algorithm that determines whether or not to store the data received for each of the determined one or more associated cache blocks based on whether or not cached data identified by the cache replacement algorithm is valid.