Managing prefetch lookahead distance based on memory access latency

A processor comprising:

• a first memory level;
• a second memory level;
• and
• a prefetcher,
• wherein the prefetcher is configured to monitor memory accesses in the first memory level,
• wherein the prefetcher is further configured to prefetch from the first memory level to the second memory level, and
• wherein the prefetcher is further configured to:
• identify, in response to memory access instructions, a pattern of addresses, wherein the pattern of addresses comprises a sub-pattern of addresses, a first address not included in the sub-pattern of addresses, and a second address not included in the sub-pattern of addresses;
• in response to a first memory access request matching the sub-pattern of addresses, prefetching, from the first memory level to the second memory level, the first address, wherein the first address is offset from the sub-pattern of addresses by a first lookahead value;
• measure a memory access latency of the first memory level;
• determine, based on the memory access latency, a second lookahead value, wherein the second lookahead value is different from the first lookahead value;
• and
• in response to a second memory access request matching the sub-pattern of addresses, prefetch the second address, wherein the second address is offset from the sub-pattern of addresses by the second lookahead value.

An apparatus comprising:

• memory;
• a cache;
• and
• a prefetcher,
• wherein the prefetcher is configured to monitor memory accesses in the memory,
• wherein the prefetcher is further configured to prefetch from the memory to the cache, and
• wherein the prefetcher is further configured to:
• identify, in response to memory access instructions, a pattern of addresses, the pattern of addresses comprising a sub-pattern of addresses, a first address not included in the sub-pattern of addresses, and a second address not included in the sub-pattern of addresses;
• in response to a first memory access request matching the sub-pattern of addresses, prefetching, from the memory to the cache, the first address, wherein the first address is offset from the sub-pattern of addresses by a first lookahead value;
• measure a memory access latency of the memory;
• determine, based on the memory access latency, a second lookahead value, wherein the second lookahead value is different from the first lookahead value;
• and
• in response to a second memory access request matching the sub-pattern of addresses, prefetch the second address, wherein the second address is offset from the sub-pattern of addresses by the second lookahead value.