US 11,379,367 B2Granted

Enhancement for activation and deactivation of memory address regions

AssigneeMicron Technology, Inc.

InventorsNicola Colella, Antonino Pollio, Hua Tan

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Abstract

Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Claims25

Dependent claims

A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

determine whether a first cache of a memory device is full based at least in part on receiving a read request for data from a block of a logical unit of the memory device, wherein the first cache of the memory device comprises a plurality of entries that are each stored to a respective slot, and wherein each entry is configured to store a mapping between logical addresses and physical addresses for a respective region of the memory device;
remove an entry from a slot of the first cache based at least in part on determining that the first cache of the memory device is full;
store, to a second cache of the memory device, an index associated with the entry removed from the slot of the first cache, wherein the index identifies a region of the memory device associated with the entry removed from the slot of the first cache;
and
transmit, to a host device, a mapping between logical addresses and physical addresses of the region associated with the entry removed from the slot of the first cache based at least in part on storing the index to the second cache of the memory device.

2 more elements

An apparatus, comprising:

a memory system comprising memory configured as a first cache;
and
a controller coupled with the memory system, wherein the controller is configured to:
determine whether the first cache is full based at least in part on receiving a read request for data from a block of a logical unit of the memory system, wherein the first cache comprises a plurality of entries that are each stored to a respective slot of the first cache, and wherein each entry is configured to store a mapping between logical addresses and physical addresses for a respective region of the memory system;
remove an entry from a slot of the first cache based at least in part on determining that the first cache is full;
store, to a second cache of the memory system, an index associated with the entry removed from the slot of the first cache, wherein the index identifies a region of the memory system associated with the entry removed from the slot of the first cache;
and
transmit, to a host device, a mapping between logical addresses and physical addresses of the region associated with the entry removed from the slot of the first cache based at least in part on storing the index to the second cache of the memory system.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/952,813Filed 19 Nov 2020
Published: US 2022/0156185 A119 May 2022
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0802
In hierarchically structured memory systems, e.g. virtual memory systems: addressing of a memory level in which the access to the desired data or…
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/0223
Addressing or allocation; Relocation: user address space allocation, e.g. contiguous or non contiguous base addressing
G06F 2212/604
Details of cache memory: details relating to cache allocation