Memory access bounds checking for a programmable atomic operator
AssigneeMicron Technology, Inc.
InventorsTony Brewer, Dean E. Walker, Chris Baronne
Life of this patent
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Abstract
Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.
Claims24
An apparatus comprising:
- an interface configured to obtain a memory interleave size indicator corresponding to a programmable atomic operator, the interface couplable to a memory controller, chiplet within a chiplet system, or a host device when in operation;
- a processor, coupled to the interface when in operation, configured to:
- execute a programmable atomic operator, the programmable atomic operator being executed with a base memory address;
- calculate a contiguous memory address range from the base memory address and the memory interleave size;
- detect that a memory request from the programmable atomic operator is outside the contiguous memory address range;
- and
- deny the memory request based on being outside of the contiguous memory address range.
A method comprising:
- executing, by a programmable atomic unit (PAU) of a memory controller, a programmable atomic operator, the programmable atomic operator being executed with a base memory address;
- obtaining a memory interleave size indicator corresponding to the programmable atomic operator;
- calculating a contiguous memory address range from the base memory address and the memory interleave size;
- detecting that a memory request from the programmable atomic operator is outside the contiguous memory address range;
- and
- denying the memory request based on being outside of the contiguous memory address range.
A non-transitory machine-readable medium including instructions that, when executed by a processor, cause the processor to perform operations comprising:
- executing a programmable atomic operator, the programmable atomic operator being executed with a base memory address;
- obtaining a memory interleave size indicator corresponding to the programmable atomic operator;
- calculating a contiguous memory address range from the base memory address and the memory interleave size;
- detecting that a memory request from the programmable atomic operator is outside the contiguous memory address range;
- and
- denying the memory request based on being outside of the contiguous memory address range.
Dependencies are inferred from the claim text.