Cache monitoring
AssigneeIntel Corporation
InventorsRen Wang, Bin Li, Andrew J. Herdrich, Tsung-Yuan C. Tai, Ramakrishna Huggahalli
Life of this patent
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Abstract
There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.
Claims21
An apparatus, comprising:
- a processor;
- a multilevel cache for use by the processor to process data, the multilevel cache to include a last-level-cache (LLC) for which a peripheral device is able to directly write data to the LLC;
- and
- circuitry to:
- monitor cache lines maintained in the LLC to detect whether at least one cache line was evicted from the LLC prior to being processed by the processor;
- and
- adjust a direct write policy to control the ability of the peripheral device to directly write data to the LLC based on whether at least one cache line was detected as being evicted from the LLC prior to being processed by the processor while the cache lines are monitored.
A method comprising:
- communicatively coupling to a last-level cache (LLC), the LLC shared by a plurality of cores of a multicore processor of a computing system, the LLC used by the plurality of cores to process data;
- communicatively coupling to a peripheral device of the computing system, the peripheral device is able to directly write data to the LLC;
- monitoring cache lines maintained in the LLC to detect whether at least one cache line was evicted from the LLC prior to being processed by at least one core from among the plurality of core;
- and
- adjusting a direct write policy to control the ability of the peripheral device to directly write data to the LLC based on whether at least one cache line was detected as being evicted from the LLC prior to being processed by the at least one core while the cache lines are monitored.
At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed by a system, cause the system to:
- communicatively couple to a last-level cache (LLC), the LLC shared by a plurality of cores of a multicore processor of a computing system, the LLC used by the plurality of cores to process data;
- communicatively couple to a peripheral device of the computing system, the peripheral device is able to directly write data to the LLC;
- monitor cache lines maintained in the LLC to detect whether at least one cache line was evicted from the LLC prior to being processed by at least one core from among the plurality of core;
- and
- adjust a direct write policy to control the ability of the peripheral device to directly write data to the LLC based on whether at least one cache line was detected as being evicted from the LLC prior to being processed by the at least one core while the cache lines are monitored.
Dependencies are inferred from the claim text.