Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMs)

An integrated circuit (IC) device comprising:

• a magnetoresistive random-access memory (MRAM) device including:
• an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells are redundant of each other;
• and
• a memory controller coupled to the array of bit cells, the memory controller is configured to, for each of the words:
• set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a value of zero is greater than the number of data bit cells in the word having a value of one,
• invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and
• revert the data bit cells to their value before the zeroes and ones were inverted.