Method for radiation hardening synchronous DRAM

A method for radiation hardening synchronous Dynamic Random Access Memory (DRAM) memory banks wherein Error Detection And Correction (EDAC) is implemented on each of said memory banks on a single chip, the method comprising:

• providing a plurality of interleaved Static Random Access Memory (SRAM) cells, wherein all logical columns for a single data bit are physically adjacent, abutting along a row, whereby said chip is less susceptible to multiple bit upsets (MBU) caused by a single charged particle due to maximum physical separation between bits in a same data word, wherein memory cells within a same data word are separated by a number of physical cells equal to a number of logical columns;
• providing a plurality of instances of bit registers configured to interface with said plurality of interleaved SRAM cells;
• providing a first column multiplexer configured to select which of said bit registers is accessed;
• providing Error Detection and Correction (EDAC) logic, configured to check Error Correction Code (ECC) during a READ burst and generate ECC during a WRITE burst for SRAM writeback during a PRECHARGE command;
• and
• providing a second column multiplexer wherein an accessed byte within the WRITE burst or the READ burst is selected from the selected bit registers of the first column multiplexer.

A system for radiation hardening synchronous Dynamic Random Access Memory (DRAM) memory cell banks wherein Error Detection And Correction (EDAC) is implemented on-chip in each bank, the system comprising:

• synchronous DRAM data writing comprising:
• inputting data to a second column multiplexer;
• providing output of the second column multiplexer to a first Pipeline Register;
• providing output of the first Pipeline Register to Error Correction Code (ECC) Generation Logic;
• providing output of the ECC Generation Logic to a second Pipeline Register;
• providing output of the second Pipeline Register to a first column multiplexer;
• providing output of the first column multiplexer to a plurality of bit registers;
• providing output of the bit registers to a SRAM Array;
• and
• ending write data flow at the SRAM Array;
• and
• synchronous DRAM data reading comprising:
• outputting data from the SRAM Array to the plurality of the bit registers;
• outputting from the plurality of bit registers to the first column multiplexer;
• outputting from the first column multiplexer to the second Pipeline Register;
• providing output from the second Pipeline Register to EDAC Logic;
• providing EDAC Logic output to the first Pipeline Register;
• providing the first Pipeline Register output to the second column multiplexer;
• and
• outputting data from the second column multiplexer.