Memory address protection circuit and method

A memory circuit comprising:

• a read-only memory (ROM) configured to store a data unit, data parity bits associated with the data unit, and address parity bits based on a write address associated with the stored data unit;
• an address port configured to receive a read address for the stored data unit;
• a first decoding circuit configured to generate a decoded write address from the read address and the address parity bits;
• and
• an error detecting circuit configured to determine if an address error exists based on a comparison of the decoded write address to the read address.

A method of operating a memory which has a single-port memory interface, the single-port memory interface including a sole address port configured to receive a read/write (RW) address;

• and a multi-port memory which has multiple address ports, the method comprising:
• receiving, at the sole address port of the single-port memory interface, a read address for a data unit stored in the multi-port memory;
• coupling the read address on the sole address port of the single-port memory interface to the multiple address ports of the multi-port memory;
• retrieving parity bits from the multi-port memory, some of the parity bits being based on the RW address for the stored data unit;
• generating, using an error detecting circuit, a decoded write address based on the read address and the retrieved parity bits;
• and
• determining, using an error detecting circuit, existence of an address error based on the decoded write address and the read address.