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US 11,379,286 B2Granted
Selective reading of memory with improved accuracy
AssigneeOvonyx Memory Technology, LLC
InventorsWayne Kinney, Gurtej S. Sandhu
Life of this patent
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Abstract
This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.
Claims13
A memory device, comprising:
- a memory array including a plurality of memory cells;
- an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array;
- and
- a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
- a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
- a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value;
- and
- a sense output circuit operable to:
- compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal;
- and
- output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.
8 more elements
A memory device, comprising:
- a memory array including a plurality of memory cells;
- an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array;
- and
- a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
- a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
- and
- a multiplexer operable to:
- receive the reference signal and the reference value read from the at least one memory cell of the plurality of memory cells;
- receive a signal indicating a detection of the one or more error conditions associated with the data read from at least one of the plurality of memory cells;
- and
- output the reference signal, or the value read from the at least one memory cell, or both to the sense output circuit based at least in part on the received signal;
- a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value;
- and
- a sense output circuit operable to:
- compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal;
- and
- output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.
14 more elements
A memory device, comprising:
- a memory array including a plurality of memory cells;
- an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array;
- and
- a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
- a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
- a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value, wherein the self-reference circuit is operable to generate the self-reference value based at least in part on a second value read from a second memory cell of the plurality of memory cells during a reference read operation that occurs before the self-reference value is generated, wherein the second value read from the second memory cell includes the self-reference value and a third value read from the second memory cell during an additional reference read operation of the second memory cell;
- and
- a sense output circuit operable to:
- compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal;
- and
- output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.
8 more elements
A memory device, comprising:
- a memory array including a plurality of memory cells;
- an error correction circuit operable to detect one or more error conditions associated with data read from at least one of the plurality of memory cells, the error correction circuit being in electronic communication with the memory array;
- and
- a sense circuit in electronic communication with the error correction circuit, wherein the sense circuit is operable in a first mode and in a second mode, the sense circuit comprising:
- a reference circuit operable to generate a reference signal and receive a reference value read from at least one memory cell of the plurality of memory cells;
- a self-reference circuit operable to receive a self-reference value read from at least one memory cell of the plurality of memory cells based at least in part on detecting the one or more error conditions associated with the reference value;
- and
- a sense output circuit operable to:
- compare the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal, wherein comparing the self-reference value read from the at least one memory cell of the plurality of memory cells and the reference signal takes longer than generating the self-reference signal;
- and
- output a data digit based at least in part on a comparison of the self-reference value read from the at least one memory cell of the plurality of memory cells and the self-reference signal.
8 more elements
Dependencies are inferred from the claim text.