US 11,379,278 B2 · Methods and apparatus for correcting out-of-order data transactions between processors

Abstract

Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

Claims20

Dependent claims

A method of processing an out-of-order transaction of digital data by a first independently operable processor apparatus, the processing for re-ordering via a second independently operable processor apparatus, the method comprising:

receiving the digital data via a data interface, the digital data comprising a plurality of data packets;
causing at least a portion of the plurality of data packets to be stored into one or more storage locations that is shared memory accessible by the first independently operable processor apparatus and the second independently operable processor apparatus, at least the one or more storage locations being described by one or more first descriptor structures corresponding to the at least a portion of the plurality of data packets, the one or more first descriptor structures residing in at least one first data structure that is associated with the one or more storage locations;
and
causing a prescribed order for the plurality of data packets to be determined, the prescribed order being indicated by one or more second descriptor structures residing in at least one second data structure, the one or more second descriptor structures being configured to enable the first independently operable processor apparatus to (i) read the one or more first descriptor structures in the prescribed order, and (ii) obtain the at least a portion of the plurality of data packets from the one or more storage locations in the prescribed order.

1 more element

A user device comprising:

a first processor apparatus and a second processor apparatus;
a memory buffer;
a shared memory structure accessible by the first and second processor apparatus;
and
a non-transitory computer-readable apparatus comprising a storage medium having a computer program stored thereon, the computer program comprising instructions configured to, when executed, cause the second processor apparatus to:
obtain, from a data source, a plurality of data packets having a first sequence order associated therewith, the shared memory structure being described by one or more first descriptor structures corresponding to at least a portion of the plurality of data packets;
transmit the plurality of data packets to the first processor apparatus, the transmission comprising provision of one or more data structures to the shared memory structure, the one or more data structures indicative of completion of the transmission of the plurality of data packets;
based at least on an evaluation of the one or more data structures, cause the first processor apparatus to:
determine a second sequence order for the plurality of data packets;
and
retrieve the plurality of data packets from the memory buffer in a rearranged order determined by the second sequence order.

8 more elements

A processor configured to re-order data transactions via an inter-processor communication (IPC) link between the processor and an independently operable processing apparatus, the processor comprising:

at least one processor core in data communication with a shared memory structure accessible by both the processor and the independently operable processing apparatus via the IPC link;
and a data interface configured for data communication between the processor and a data source;
wherein the processor is configured to:
receive data packets via the data interface in a first order;
and
write, in the first order, the received data packets to one or more storage structures residing in the shared memory structure, the received data packets being described by one or more first data structures in the shared memory structure corresponding to at least a portion of the received data packets;
based at least on a determination that the first order associated with the received data packets is out of order, identify a second order for the received data packets;
and
provide one or more second data structures to the shared memory structure, the one or more second data structures being indicative of the second order for the received data packets;
and
wherein the provision of the one or more second data structures enables the independently operable processing apparatus to retrieve the data packets in the second order based at least on a read of the one or more second data structures.

8 more elements

Dependencies are inferred from the claim text.

Methods and apparatus for correcting out-of-order data transactions between processors

Life of this patent

Methods and apparatus for correcting out-of-order data transactions between processors

Life of this patent

Abstract

Claims20