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US 11,379,238 B2Granted
Processor authentication method through signed instruction
AssigneesProton World International N.V., STMicroelectronics (Rousset) SAS
InventorsMichael Peeters, Fabrice Marinet
Life of this patent
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Abstract
The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
Claims20
A method, comprising:
- decoding a first opcode into a decoded instruction and a plurality of decoded operands;
- receiving, on a first terminal of an arithmetic and logic unit of a processor, a decoded operand of the plurality of decoded operands;
- generating a first instruction by combining the decoded instruction with signature data, the signature data being an output data of the arithmetic and logic unit prior to the generating the first instruction;
- receiving, on a second terminal of the arithmetic and logic unit, the first instruction;
- and
- authenticating the processor based on a result of the arithmetic and logic unit processing the first instruction.
3 more elements
A processor, comprising:
- a combination circuit that operates to generate a first instruction by combining a second instruction of a first opcode with signature data;
- and
- an arithmetic and logic unit having a first terminal and a second terminal, the first terminal being configured to receive a first operand of the first opcode, and the second terminal being configured to receive the first instruction;
- wherein the signature data is a processing result of the arithmetic and logic unit with respect to a second opcode that is received by the processor before the first opcode;
- and
- wherein the processor is configured to be authenticated based on a result of the arithmetic and logic unit processing the first instruction.
3 more elements
An integrated circuit, comprising:
- a decoding circuitry that operates to decode a first opcode into a decoded instruction and a plurality of decoded operands;
- a multiplexer circuitry that operates to select a first decoded operand from the plurality of decoded operands;
- a combination circuitry that operates to generate a signed instruction by combining the decoded instruction and signature data;
- and
- an arithmetic and logic circuitry that operates to calculate a first result based on the first decoded operand and the signed instruction;
- wherein the signature data includes a second result calculated by the arithmetic and logic circuitry prior to the first result;
- and
- wherein the first result is configured to authenticate the integrated circuit.
5 more elements
Dependencies are inferred from the claim text.