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US 11,379,237 B2Granted
Variable-length-instruction processing modes
AssigneeArm Limited
InventorSimon John Craske
Life of this patent
Estimating the term…
Abstract
A data processing apparatus (2) operates in a first mode of operation having a first set of processing circuitry (8, 12, 18, 20, 22) ready to perform processing operations and in a second mode of operation having a second set of processing circuitry (8, 12, 14, 18, 20, 22, 24) ready to perform processing operations. A first proper subset (32) of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. A second proper subset (34) of program instructions within the instruction set are required to be processed by the processor operating in the second mode. Processing circuitry (14, 24) which is inactive in a mode of operation may be placed into a low power state.
Claims20
Apparatus for processing data, comprising:
- a processor to perform processing operations upon operands stored within a register file of said processor and as specified by program instructions of an instruction set, said processor comprising fetch circuitry for fetching said program instructions for execution from a memory and decoder circuitry, coupled to said fetch circuitry, for decoding said fetched program instructions, and operating in at least a first mode of operation using a first set of active processing circuitry to perform processing operations upon the operands stored within the register file and as specified by the program instructions of the instruction set and a second mode of operation using a second set of active processing circuitry to perform alternative implementations of the processing operations upon the operands stored within the register file and as specified by the program instructions of the instruction set, said second set of active processing circuitry different from said first set of active processing circuitry;
- wherein, when fetching said program instructions and decoding said fetched program instructions:
- said processor is configured to process a first proper subset of 16/32-bit program instructions within said instruction set by operating in a selectable one of said first mode and said second mode;
- and
- said processor is configured to process a second proper subset of 32/64-bit program instructions within said instruction set by operating in said second mode,
- wherein in the first mode said 16/32-bit program instructions of the first proper subset are 16-bit and in the second mode said 32/64-bit program instructions of the second proper subset are 32-bit, or said 16/32-bit program instructions of the first proper subset are 32-bit and said 32/64-bit program instructions of the second proper subset are 64-bit, and
- wherein said second set of active processing circuitry comprises first decoder circuitry to decode said 16/32-bit program instructions of said first proper subset and second decoder circuitry to decode said 32/64-bit program instructions of said second proper subset and said first set of active processing circuitry comprises said first decoder circuitry and excludes said second decoder circuitry.
4 more elements
Apparatus for processing data, comprising:
- processing means for performing processing operations upon operands stored within a register file of said processor means, comprising means for fetching said program instructions for execution from a memory and means for decoding, coupled to said means for fetching, for decoding said fetched program instructions, and as specified by program instructions of an instruction set, said processing means operating in at least a first mode of operation using a first set of active processing means for performing processing operations upon the operands stored within the register file and as specified by the program instructions of the instruction set and a second mode of operation using a second set of active processing means for performing alternative implementations of the processing operations upon the operands stored within the register file and as specified by the program instructions of the instruction set, said second set of active processing means different from said first set of active processing means;
- wherein, when fetching said program instructions and decoding said fetched program instructions:
- said processing means is configured to process a first proper subset of 16/32-bit program instructions within said instruction set by operating in a selectable one of said first mode and said second mode;
- and
- said processing means is configured to process a second proper subset of 32/64-bit program instructions within said instruction set by operating in said second mode,
- wherein in the first mode said 16/32-bit program instructions of the first proper subset are 16-bit and in the second mode said 32/64-bit program instructions of the second proper subset are 32-bit, or said 16/32-bit program instructions of the first proper subset are 32-bit and said 32/64-bit program instructions of the second proper subset are 64-bit, and
- wherein said second set of active processing means comprises first decoder means to decode said 16/32-bit program instructions of said first proper subset and second decoder means to decode said 32/64-bit program instructions of said second proper subset and said first set of active processing means comprises said first decoder means and excludes said second decoder means.
4 more elements
A method of processing data, comprising:
- performing processing operations upon operands stored within a register file of a processor, comprising fetch circuitry for fetching said program instructions for execution from a memory and decoder circuitry, coupled to said fetch circuitry, for decoding said fetched program instructions, and as specified by program instructions of an instruction set using at least a first mode of operation using a first set of active processing circuitry for performing processing operations upon the operands stored within the register file and as specified by the program instructions of the instruction set and a second mode of operation using a second set of active processing circuitry for performing alternative implementations of the processing operations upon the operands stored within the register file and as specified by the program instructions of the instruction set, said second set of active processing circuitry different from said first set of active processing circuitry;
- wherein, when fetching said program instructions and decoding said fetched program instructions:
- processing with said processor a first proper subset of 16/32-bit program instructions within said instruction set using a selectable one of said first mode and said second mode;
- and
- processing with said processor a second proper subset of 32/64-bit program instructions within said instruction set using said second mode,
- wherein in the first mode said 16/32-bit program instructions of the first proper subset are 16-bit and in the second mode said 32/64-bit program instructions of the second proper subset are 32-bit, or said 16/32-bit program instructions of the first proper subset are 32-bit and said 32/64-bit program instructions of the second proper subset are 64-bit, and
- wherein said second set of active processing circuitry comprises first decoder circuitry to decode said 16/32-bit program instructions of said first proper subset and second decoder circuitry to decode said 32/64-bit program instructions of said second proper subset and said first set of active processing circuitry comprises said first decoder circuitry and excludes said second decoder circuitry.
4 more elements
Dependencies are inferred from the claim text.