Apparatus and method for adaptable and efficient lane-wise tensor processing

A method comprising:

• scheduling matrix operations responsive to a matrix multiplication instruction;
• performing parallel portions of the matrix operations across multiple lanes, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are stored in registers of that lane;
• and
• broadcasting one or more invariant matrix blocks including the block of the first matrix to at least one of different registers of a lane and different registers across different lanes,
• wherein each lane further comprises multipliers to multiple matrix blocks of the first and second matrices, and wherein one or more adders and accumulators to accumulate results from the multiplication, and wherein interconnections between the multipliers and registers are reconfigured in response to different matrix dimensions of the first, second, or third matrices.

A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, is capable of causing the machine to perform:

• scheduling matrix operations responsive to a matrix multiplication instruction;
• performing parallel portions of the matrix operations across multiple lanes, wherein a lane comprise an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are stored in registers of the lane;
• and
• broadcasting one or more invariant matrix blocks including the block of the first matrix to at least one of different registers of the lane and different registers across different lanes,
• wherein each lane further comprises multipliers to multiple matrix blocks of the first and second matrices, and wherein one or more adders and accumulators to accumulate results from the multiplication, and wherein interconnections between the multipliers and registers are reconfigured in response to different matrix dimensions of the first, second, or third matrices.