Dynamic random access memory (DRAM) bandwidth increase without per pin bandwidth increase
AssigneeSamsung Electronics Co., Ltd.
InventorPhilip Enrique Madrid
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory (DRAM) includes first and second data buses, and first and second command and address (C/A) buses. The first data bus conveys a write data to the DRAM. The second data bus conveys read data from the DRAM. The first and second C/A buses are respectively associated with the first and second data buses. In one embodiment, the first data bus conveys the write data to a first bank of memory of the DRAM simultaneously as the second data bus conveys the read data from a second bank of memory of the DRAM. In another embodiment, the first data bus conveys the write data to a first rank of memory of the DRAM simultaneously as the second data bus conveys read data from a second rank of memory of the DRAM.
Claims18
A dynamic random access memory (DRAM), comprising:
- a first data bus that conveys a first type of data in a first direction with respect to the DRAM;
- a first command and address bus that is associated with the first data bus;
- a second data bus that conveys a second type of data in a second direction with respect to the DRAM, the second data bus being separate from the first data bus;
- and
- a second command and address bus that is associated with the second data bus, the second command and address bus being separate from the first command and address bus.
A dynamic random access memory (DRAM), comprising:
- a first rank of memory and a second rank of memory;
- a first data bus that conveys a first type of data in a first direction with respect to the first rank of memory;
- and
- a second data bus that conveys a second type of data in a second direction with respect to the second rank of memory, the second data bus being separate from the first data bus,
- the first data bus conveying the first type of data with respect to the first rank of memory simultaneously as the second data bus conveys the second type of data with respect to the second rank of memory.
A dynamic random access memory (DRAM), comprising:
- a first bank of memory and a second bank of memory;
- a first data bus that conveys a first type of data in a first direction with respect to the DRAM;
- a first command and address bus that is associated with the first data bus;
- a second data bus that conveys a second type of data in a second direction with respect to the DRAM, the second data bus being separate from the first data bus;
- and
- a second command and address bus that is associated with the second data bus, the second command and address bus being separate from the first command and address bus,
- the first data bus conveying the first type of data with respect to the first bank of memory simultaneously as the second data bus conveys the second type of data with respect to the second bank of memory.
Dependencies are inferred from the claim text.