Memory device including a processing circuit, memory controller controlling the memory device and memory system including the memory device

A memory controller comprising:

• a request queue configured to store one or more requests, each request including a memory request or a Process In Memory (PIM) request, the memory request including a read request to a memory device or a write request to the memory device, and the PIM request requiring a processing operation in the memory device;
• a command generator configured to receive a request from the request queue, to generate a memory command when the received request includes a memory request, and to generate a PIM command when the received request includes a PIM request;
• a command queue configured to store memory commands and PIM commands generated by the command generator;
• a command scheduler configured to control an output order or an output timing of the memory commands and the PIM commands stored in the command queue;
• a PIM decoder configured to generate a PIM request from a PIM instruction;
• and
• a PIM instruction queue configured to store the PIM instruction,
• wherein the PIM instruction is included in write data of a write request and the write request includes PIM information indicating whether a PIM instruction is included in the write request, and
• wherein the memory controller further comprises a path selection circuit configured to send the write request to the request queue when the PIM information has a first state and to the PIM instruction queue when the PIM information has a second state.

A memory device comprising:

• a command decoder configured to decode a command, the command including a memory command or a PIM command, the memory command corresponding to a read or a write operation in the memory device, and the PIM command corresponding to a processing operation in the memory device;
• a bank storing data;
• an input/output (IO) buffer configured to input data to or output data from the memory device;
• a shared bus configured to transfer data between the bank and the IO buffer;
• and
• a processing circuit coupled to the shared bus and to the bank, and configured to perform a processing operation as directed by the command decoder,
• wherein the bank is controlled by the command decoder to perform a read or write operation according to a memory command while the processing circuit performs a processing operation according to a PIM command.

A memory system:

• comprising:
• a memory device;
• and
• a memory controller configured to:
• receive a request,
• generate a memory command from the request when the request includes a memory request, the memory request including a read request or a write request for the memory device,
• generate a PIM command from the request when the request includes a PIM request, the PIM request requiring a processing operation in the memory device, and
• schedule the PIM command together with the memory command,
• wherein the memory device performs a data read operation or a data write operation in response to a memory command from the memory controller and performs a processing operation in response to a PIM command from the memory controller, and
• wherein the memory device performs the data read operation or the data write operation while the memory device performs the processing operation.