Drift detection in timing signal forwarded from memory controller to memory device
AssigneeRambus Inc.
InventorsJun Kim, Pak Shing Chau, Wayne S. Richardson
Life of this patent
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Abstract
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
Claims21
A memory device comprising:
- a memory core to store data;
- a first circuit to receive, from a memory controller, a first timing signal having a first frequency, wherein the first timing signal is to be used to time a data transfer operation with the memory core;
- a second circuit that mimics a timing delay through a clock distribution circuit in the memory device, wherein the clock distribution circuit uses the first timing signal for the data transfer operation, the second circuit to determine a phase delay that occurs on a second timing signal that is received from the memory controller and has a second frequency that is different than the first frequency of the first timing signal using a plurality of different delay elements, and the second circuit generating information indicative of the phase delay occurring on the second timing signal in the memory device using the plurality of different delay elements;
- and
- a transmitter to output the information to the memory controller.
A method of operating a memory device including a memory core that stores data, the method comprising:
- receiving from a memory controller a first timing signal having a first frequency, the first timing signal provided to the memory core for use in a data transfer operation with the memory core;
- mimicking a timing delay through a clock distribution circuit in the memory device that uses the first timing signal for the data transfer operation to determine a phase delay that occurs on a second timing signal that is received from the memory controller and has a second frequency that is different than the first frequency of the first timing signal, the timing delay mimicked using a plurality of different delay elements that each delay the second timing signal by a respective delay ;
- generating information indicative of the phase delay occurring on the second timing signal in the memory device using the plurality of different delay elements;
- and
- outputting the information to the memory controller.
A memory device comprising:
- a means for storing data;
- a means for receiving from a memory controller a first timing signal having a first frequency, the first circuit providing the first timing signal to the memory core for use in a data transfer operation with the memory core;
- a means for mimicking a timing delay through a clock distribution circuit in the memory device that uses the first timing signal for the data transfer operation, the means for mimicking the timing delay to determine a phase delay that occurs on a second timing signal that is received from the memory controller and has a second frequency that is different than the first frequency of the first timing signal using a plurality of different delay elements that each delay the second timing signal by a respective delay, and the means for mimicking the timing delay is further for generating information indicative of the phase delay occurring on the second timing signal in the memory device using the plurality of different delay elements;
- and
- a means for outputting the information to the memory controller.
Dependencies are inferred from the claim text.