Voltage regulator circuit with current limiter stage

A voltage regulator circuit, comprising:

• an amplifier stage configured to output a DC voltage based on a reference voltage and feedback of an output voltage of the voltage regulator circuit;
• and
• a current limiter stage including:
• a source follower field effect transistor (FET), wherein a gate of the source follower FET is electrically connected to an output of the amplifier stage,
• an output FET, wherein a gate of the output FET is electrically connected to the source of the source follower FET, wherein the source of the output FET is electrically connected to a power supply node, and wherein the drain of the output FET is electrically connected to an output node, and
• a current control stage electrically intermediate the power supply node and the drain of the source follower FET;
• wherein the current limiter stage is configured to operate in a quiescent operating mode and an overload operating mode, such that
• in the quiescent operating mode, the source follower FET and the output FET are configured to operate as a buffer stage that forms a closed feedback loop to feedback the output voltage of the voltage regulator circuit to an input of the amplifier stage, and
• in the overload operating mode, the source follower FET is configured to act as a triode switch that electrically connects the current control stage to the gate of the output FET such that a current mirror forms between the current control stage and the output FET so that an output current of the voltage regulator circuit is clamped to a designated current controlled by the current control stage.

A method for limiting current in a voltage regulator circuit comprising an amplifier stage and a current limiter stage, the current limiter stage being configured to act as a buffer in a quiescent operating mode and as a current mirror in an overload operating mode, the method comprising:

• amplifying, via the amplifier stage, an output voltage of the voltage regulator circuit through a feedback loop, such that an output of the amplifier stage is set to a reference voltage based on an output current of the voltage regulator circuit being less than a threshold current in the quiescent operating mode, and such that the output of the amplifier stage is set to zero volts based on the output current of the voltage regulator circuit being greater than the threshold current in the overload operating mode;
• buffering, via the current limiter stage, the output of the amplifier stage based on the output of the amplifier stage being set to the reference voltage in the quiescent operating mode when the current limiter stage is operating as the buffer;
• and
• clamping, via the current limiter stage when the current limiter stage is acting as the current mirror in the overload operating mode, the output current of the voltage regulator circuit to a designated current.