US 11,378,623 B2Granted

Diagnostic enhancement for multiple instances of identical structures

AssigneeInternational Business Machines Corporation

InventorsSteven Michael Douskey, Orazio Pasquale Forlenza, Mary P. Kusko, Franco Motika, Gerard Michael Salem

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Abstract

A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.

Claims18

Dependent claims

A method comprising:

executing a test against a first structure and a second structure of a built-in self-test circuit, each of the first and second structures comprising a plurality of latches arranged as a plurality of stump chains;
unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure;
generating a first signature based on the first result and a second signature based on the second result;
determining that the first structure failed the test based on the first signature mismatching a reference signature and that the second structure passed the test based on the second signature matching the reference signature;
comparing the first result to the second result to identify a mismatch between the first result and the second result;
and
determining a faulty latch in the first structure based on the mismatch.

4 more elements

An apparatus comprising:

a memory;
and
a hardware processor communicatively coupled to the memory, the hardware processor configured to:
execute a test against a first structure and a second structure of a built-in self-test circuit, each of the first and second structures comprising a plurality of latches arranged as a plurality of stump chains;
unload a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure;
generate a first signature based on the first result and a second signature based on the second result;
determine that the first structure failed the test based on the first signature mismatching a reference signature and that the second structure passed the test based on the second signature matching the reference signature;
compare the first result to the second result to identify a mismatch between the first result and the second result;
and
determine a faulty latch in the first structure based on the mismatch.

7 more elements

A system comprising:

a built-in self-test circuit;
and
a test engine comprising a hardware processor configured to:
execute a test against a first structure and a second structure of the built-in self-test circuit, each of the first and second structures comprising a plurality of latches arranged as a plurality of stump chains;
toggle multiple input signature registers of the first and second structures to operate as shift registers;
unload a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure;
generate a first signature based on the first result and a second signature based on the second result;
determine that the first structure failed the test based on the first signature mismatching a reference signature and that the second structure passed the test based on the second signature matching the reference signature;
compare the first result to the second result to identify a mismatch between the first result and the second result;
and
determine a faulty latch in the first structure based on the mismatch.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/115,434Filed 8 Dec 2020
Published: US 2022/0178996 A19 Jun 2022
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G01R 31/318547
Scanning methods, algorithms and patterns: data generators or compressors
G01R 31/3183
Functional testing: generation of test inputs, e.g. test vectors, patterns or sequences
G01R 31/318538
Scan chain arrangements, e.g. connections, test bus, analog signals: topological or mechanical aspects
G01R 31/318566
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: comparators; Diagnosing the device under test