US 11,378,622 B1Granted

Methods and systems for single-event upset fault injection testing

AssigneeRaytheon Company

InventorsPatrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack

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Abstract

Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.

Claims20

Dependent claims

A fault injection test system for field programmable gate array (FPGA) devices comprising:

a test interface module including a first communications interface for a FPGA device under test (DUT) and a second communications interface for a reference FPGA device, the test interface module being arranged to:
image a configuration RAM (CRAM) of the FPGA DUT, via the first communications interface, with a first configuration image to implement a first operational function in the FPGA DUT, the CRAM including a plurality of CRAM bits,
image a CRAM of the reference FPGA device, via the second communications interface, with the first configuration image to implement the first operational function in the reference FPGA device, and
log error event data associated with one or more error events stored in one or more error registers;
a configuration module including a third communications interface to the FPGA DUT, the configuration module arranged to inject a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating based on the first operational function;
and
a monitor module including a fourth communications interface for the FPGA DUT and in communications with the reference FPGA device, the monitor module including the one or more error registers, the monitor module arranged to:
monitor operations of the FPGA DUT and the reference FPGA device while the FPGA DUT and the reference FPGA devices are operating concurrently,
compare one or more outputs of the FPGA DUT with one or more outputs of the reference FPGA device during concurrent operations, and
when there is a mismatch between the one or more outputs of the FPGA DUT and the one or more outputs of the reference FPGA, determine that the one or more error events have occurred within the FPGA DUT and store the one or more error events in the one or more error registers;
and
the configuration module in communication with the test interface module and the monitor module being further arranged to:
instruct the test interface module to image the FPGA DUT and reference FPGA device and initiate concurrent operations of the FPGA DUT and the reference FPGA device,
instruct the monitor module to monitor the concurrent operations of the FPGA DUT and the reference FPGA device while the configuration module injects the plurality of single event upsets into the portion of the plurality of CRAM bits of the FPGA DUT, and
store the error event data associated with the one or more error events in an error log.

12 more elements

A method for performing fault injection testing for field programmable gate array (FPGA) devices comprising:

interfacing, via a first communications interface, with a FPGA device under test (DUT);
imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT, the CRAM including a plurality of CRAM bits;
injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating based on the operational function;
monitoring, via a second communications interface, operations of the FPGA DUT;
monitoring concurrently with monitoring the operations of the FPGA DUT, via a third communications interface, operations of a reference FPGA device, wherein a CRAM of the reference FPGA device is configured with the first configuration image and operating based on the first operational function;
comparing one or more outputs of the FPGA DUT with one or more outputs of the reference FPGA device during concurrent operations,
when there is a mismatch between the one or more outputs of the FPGA DUT and the one or more outputs of the reference FPGA, determining that one or more error events have occurred within the FPGA DUT;
and
in response to determining that the one or more error events have occurred within the FPGA DUT, storing at least one of the one or more error events and CRAM location data associated with corresponding single event upsets in an error log.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/141,872Filed 5 Jan 2021
Published: US 2022/0214951 A17 Jul 2022
Granted: 5 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 11/273
Functional testing: tester hardware, i.e. output processing circuits
G01R 31/31701
Testing of digital circuits: arrangements for setting the Unit Under Test [UUT] in a test mode
G01R 31/31703
Testing of digital circuits: comparison aspects, e.g. signature analysis, comparators
G01R 31/31816
Functional testing: soft error testing; Soft error rate evaluation; Single event testing