Systems and methods for bit level signal processing
AssigneeZte Corporation
InventorChen Huang
Life of this patent
Estimating the term…
Abstract
This disclosure relates generally to wireless communications and, more particularly, to systems and methods for bit level processing to produce a scrambled data bit sequence that, after modulation, may produce a symbol sequence that matches a symbol sequence produced by symbol spreading. In one embodiment, a method performed by a communication device includes: encoding user data to produce a first data bit sequence; generating a result bit sequence based on a first scrambling bit sequence and the first data bit sequence; and transmitting a signal based on a scrambled data bit sequence scrambled with the result bit sequence.
Claims18
A method performed by a communication device, comprising:
- encoding user data to produce a first data bit sequence;
- generating a result bit sequence based on a first scrambling bit sequence and the first data bit sequence;
- transmitting a signal based on a scrambled data bit sequence scrambled with the result bit sequence;
- performing an exclusive OR (XOR) operation on two adjacent most significant bits of the first scrambling bit sequence to produce a scrambling bit value;
- performing the XOR operation on each two adjacent bits of the first data bit sequence to produce a second data bit sequence;
- and
- performing an AND operation on the scrambling bit value and the second data bit sequence to produce the result bit sequence.
A method performed by a communication node, comprising:
- encoding user data to produce a first data bit sequence;
- generating a result bit sequence based on a first scrambling bit sequence and the first data bit sequence;
- transmitting a signal based on a scrambled data bit sequence scrambled with the result bit sequences;
- performing an exclusive OR (XOR) operation on two adjacent most significant bits of the first scrambling bit sequence to produce a scrambling bit value;
- performing the XOR operation on each two adjacent bits of the first data bit sequence to produce a second data bit sequence;
- and
- performing an AND operation on the scrambling bit value and the second data bit sequence to produce the result bit sequence.
Dependencies are inferred from the claim text.