# US 11,362,266 B2 · Magneto resistive memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,362,266 B2 - Document ID: US11362266B2 - Status: Granted - Kind: B2 - Application number: 17/179,084 - Filed: 2021-02-18 - Published: 2022-01-27 - Granted: 2022-06-14 - Earliest claimed: 2020-07-23 - Assignees: Antaios - Applicants: Antaios - Inventors: Marc Drouard; Jérémie Vigier; Jérémy Brun-Picard - Web page: https://patentgrep.com/patent/US11362266B2 ## CPC - G11C 11/18: using Hall-effect devices - H10N 52/80: Constructional details - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1675: {Writing or programming circuits or methods} - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - H10B 61/20: {comprising components having three or more electrodes, e.g. transistors} - H10N 50/10: Magnetoresistive devices - H10N 50/80: Constructional details - H10N 50/85: Materials of the active region - H10N 52/00: Hall-effect devices (integrated devices or assemblies of multiple devices H10N59/00) - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing. ## Claims ### Claim 1 A memory device comprising: a substrate (S) defining a main plane; a plurality of memory cells (1) each comprising a SOT current layer (3) disposed in the main plane of the substrate (S) and a magnetic tunnel junction (2) residing on the SOT current layer (3); a bit line (BL) and a source line (SL) to flow a write current in a write path including the SOT current layer (3) of a selected memory cell (1); wherein the source line (SL) comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction (2) of the selected memory cell (1) for assisting the switching of the cell state when the write current is flowing. ### Claim 2 (depends on 1) Memory device according to claim 1, wherein the memory cells (1) are arranged on the substrate to form a first column and the source line (SL) extends along the first column of memory cells. ### Claim 3 (depends on 1) Memory device according to claim 1, wherein the source line (SL) comprises a first line (SL1) made of the magnetic conductive material and a second line (SL2), electrically connected to the first line (SL1), made of conductive non-magnetic material. ### Claim 4 (depends on 1) Memory device according to claim 1, wherein the first and second lines (SL1, SL2) are disposed in respective planes parallel to the main plane, and are electrically connected by a plurality of conductive vias (SLv). ### Claim 5 (depends on 3) Memory device according to claim 3, further comprising a second column of memory cells (1) parallel to the first column of memory cells (1), the source line (SL) extending in-between the first and the second column. ### Claim 6 (depends on 1) Memory device according to claim 1, wherein the SOT current layer (3) of each memory cell (1) is contacting the first line (SL1). ### Claim 7 (depends on 6) Memory device according to claim 6, wherein the first line (SL1) is configured as a single strip, and the SOT current layers (3) of the first and second column of memory cells (1) are respectively contacting two opposed lateral sides of the single strip. ### Claim 8 (depends on 6) Memory device according to claim 6, wherein the first line (SL) is configured as two parallels strips, each strip being connected to the second line (SL2) by a plurality of conductive vias, and the SOT current layers (3) of the first and second column of memory cells (1) are respectively contacting the two parallels strips. ### Claim 9 (depends on 6) Memory device according to claim 6, further comprising a plurality of enhancing patterns (P) made of conductive magnetic material, each enhancing patterns (P) being disposed in a write path between the bit line (BL) and the SOT current layer (3) of a memory cell (1), in electrical contact with this layer (3). ### Claim 10 (depends on 9) Memory device according to claim 9, wherein the enhancing pattern (P) is presenting a magnetization parallel to the magnetization of the source line (SL) and wherein, for each memory cell (1), the magnetic tunnel junction (2) is residing on a first face of the SOT current layer (3), an enhancing pattern (P) and the source line (SL) electrically contacting a second face of the SOT current layer (3), opposing the first face. ### Claim 11 (depends on 10) Memory device according to claim 10, further comprising an additional line (L′) and/or an additional pattern (P′) both made of magnetic material, disposed on the first face of the SOT current layer (3). ### Claim 12 (depends on 9) Memory device according to claim 9, wherein the each enhancing pattern (P) is presenting a magnetization parallel to the magnetization of the source line (SL) and wherein, for each memory cell (1), an enhancing pattern (P) and the source line (SL) are respectively contacting the two lateral sides of the SOT current layer (3). ### Claim 13 (depends on 6) Memory device according to claim 6, wherein for each memory cell (1), and enhancing block (B) is disposed on the magnetic tunnel junction (2) and is presenting a magnetization antiparallel to the magnetization of the magnetic material of the source line (SL). ### Claim 14 (depends on 1) The memory device according to claim 1, wherein the magnetic bias field is extending parallel to the main plane. ### Claim 15 (depends on 1) The memory device according to claim 1, wherein the magnetic bias field is extending perpendicular to the main plane.