Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions

A resistive thyristor with a high holding voltage, comprising:

• a PNP bipolar transistor;
• a NPN bipolar transistor cross-coupled with the PNP bipolar transistor;
• a first conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor;
• a p-type semiconductor well region (PW) configured to operate as a base of the NPN bipolar transistor and as the collector of the PNP bipolar transistor;
• an n-type semiconductor well region (NW) adjacent to the first PW and configured to operate as a base of the PNP bipolar transistor and as the collector of the NPN bipolar transistor;
• a trench isolation region between the NW and the PW;
• a first p-type active (P+) region formed in the NW and configured to operate as an emitter of the PNP bipolar transistor;
• a first n-type active (N+) region formed in the NW;
• a second N+ region formed in the PW and configured to operate as an emitter of the NPN bipolar transistor;
• a second P+ region formed in the PW;
• a second conductor connecting the second P+ region to the second N+ region;
• and
• a third conductor connecting the first P+ region and the first N+ region.

A semiconductor die comprising:

• a first pad and a second pad;
• and
• a stacked thyristor protection structure electrically connected between the first pad and the second pad, the stacked thyristor protection structure comprising:
• a protection device having a holding voltage;
• and
• a first resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, a first conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor, a p-type semiconductor well region (PW) configured to operate as a base of the NPN bipolar transistor and as the collector of the PNP bipolar transistor, an n-type semiconductor well region (NW) adjacent to the first PW and configured to operate as a base of the PNP bipolar transistor and as the collector of the NPN bipolar transistor, a trench isolation region between the NW and the PW, a first p-type active (P+) region formed in the NW and configured to operate as an emitter of the PNP bipolar transistor, a first n-type active (N+) region formed in the NW, a second N+ region formed in the PW and configured to operate as an emitter of the NPN bipolar transistor, a second P+ region formed in the PW, a second conductor connecting the second P+ region to the second N+ region, and a third conductor connecting the first P+ region and the first N+ region to a first terminal of the protection device.