Neural processing accelerator

A system for calculating, the system comprising:

• a plurality of processing element circuits;
• a communication fabric comprising a plurality of node circuits;
• and
• a scratch memory,
• the scratch memory being connected to the processing element circuits through the communication fabric,
• one or more of the of the node circuits comprising a plurality of node link circuits,
• a first node link circuit of the plurality of node link circuits of a first node circuit of the plurality of node circuits having a plurality of inputs and an output, and comprising:
• a data register, and
• a configuration register configured to store a configuration value,
• the first node link circuit being configured to receive, at the inputs, a plurality of respective data words, each of the data words having a control portion and a data portion, and:
• when one of the data words has a control portion identifying it as a node link configuration word, to store the data portion of the node link configuration word in the configuration register;
• and
• when none of the data words is a node link configuration word:
• to send a data word from one of the inputs to the data register, and/or
• to send a data word from one of the inputs to the output, and/or
• to send a data word from the data register to the output, depending on the configuration value.

A method for calculating, the method comprising:

• configuring a processing module, the processing module comprising:
• a plurality of processing element circuits;
• a communication fabric comprising a plurality of node link circuits each having a plurality of inputs and an output;
• and
• a scratch memory,
• the configuring comprising:
• sending, by the scratch memory, a plurality of node link configuration words, each addressed to a node link circuit of the plurality of node link circuits;
• receiving, by a first node link circuit of the plurality of node link circuits, a data word addressed to the first node link circuit, the first node link circuit having an output connected to an input of a first processing element circuit of the plurality of processing element circuits;
• setting, by the first node link circuit, a configuration of the first node link circuit, to cause the first node link circuit to forward data words received at a first input of the first node link circuit to the output of the first node link circuit;
• receiving, by the first input of the first node link circuit, a processing element configuration word;
• sending, by the first input of the first node link circuit, the processing element configuration word to the first processing element circuit;
• and
• storing, by the first processing element circuit, in a control register of the first processing element circuit, a data portion of the processing element configuration word.