Method for programming a phase-change memory device of differential type, phase-change memory device, and electronic system

A differential-type phase-change memory, comprising:

• a plurality of phase-change memory cells;
• a first programming driver of respective phase-change memory cells;
• a second programming driver of respective phase-change memory cells;
• a first group of direct main bitlines and respective complementary main bitlines coupled to the first programming driver through respective direct and complementary selectors;
• a second group of direct main bitlines and respective complementary main bitlines coupled to the second programming driver through respective direct and complementary selectors;
• the plurality of phase-change memory cells including first direct and complementary memory cells coupled to the direct and respectively complementary main bitlines of the first group and associated with the first programming driver, and second direct and complementary memory cells coupled to the direct and respectively complementary main bitlines of the second group and associated with the second programming driver;
• and
• each of the first direct and complementary memory cells associated with the first programming driver being uniquely addressable by local bitlines and wordlines, and each of the second direct and complementary memory cells associated with the second programming driver being uniquely addressable by respective local bitlines and wordlines,
• wherein the phase-change memory device is configured for:
• in a first operating condition associated with a first time interval:
• (a) for each between the first and second groups, activating the direct selectors or the complementary selectors so as to electrically connect each direct or, respectively, complementary main bitline, to the first and second programming drivers thereof;
• (b) addressing, through the local bitlines and wordlines coupled to the first memory cells associated with the first programming driver, a direct memory cell or the respective complementary memory cell, establishing a conductive path between the first programming driver and the first memory cell addressed;
• (c) addressing, through the local bitlines and wordlines coupled to the second memory cells associated with the second programming driver, a direct memory cell or the respective complementary memory cell, establishing a conductive path between the second programming driver and the second memory cell addressed;
• and
• (d) supplying, through the first and second programming drivers, a first programming current, of a same type between SET and RESET currents, together with the first and second memory cells addressed in the steps (b) and (c);
• and
• in a second operating condition associated with a second time interval different from the first time interval:
• (e) for each between the first and second groups, activating the others between the direct selectors or the complementary selectors activated in the step (a), so as to electrically connect each direct, or, respectively, complementary main bitline, to the first and second programming drivers thereof;
• (f) addressing, through the local bitlines and wordlines coupled to the first memory cells associated with the first programming driver, the other direct or complementary memory cell with respect to that addressed in the step (b);
• (g) addressing, through the local bitlines and wordlines coupled to the second memory cells associated with the second programming driver, the other direct or complementary memory cell with respect to that addressed in the step (c);
• and
• (h) supplying, through the first and second programming drivers, a second programming current, of the other type between SET and RESET currents, together with the first and second memory cells addressed in the steps (f) and (g).

An electronic system, comprising:

• a bus;
• a controller coupled to the bus;
• an input/output device coupled to the bus;
• a wireless interface coupled to the bus;
• a random access memory coupled to the bus;
• and
• a differential-type phase-change memory device comprising:
• a plurality of phase-change memory cells;
• a first programming driver of respective phase-change memory cells;
• a second programming driver of respective phase-change memory cells;
• a first group of direct main bitlines and respective complementary main bitlines coupled to the first programming driver through respective direct and complementary selectors;
• a second group of direct main bitlines and respective complementary main bitlines coupled to the second programming driver through respective direct and complementary selectors;
• the plurality of phase-change memory cells including first direct and complementary memory cells coupled to the direct and respectively complementary main bitlines of the first group and associated with the first programming driver, and second direct and complementary memory cells coupled to the direct and respectively complementary main bitlines of the second group and associated with the second programming driver;
• and
• each of the first and second direct and complementary memory cells associated with the first programming driver being uniquely addressable by local bitlines and wordlines, and each of the first and second direct and complementary memory cells associated with the second programming driver being uniquely addressable by respective local bitlines and wordlines,
• wherein the phase-change memory device is configured for:
• in a first operating condition associated with a first time interval:
• (a) for each between the first and second groups, activating the direct selectors or the complementary selectors so as to electrically connect each direct or, respectively, complementary main bitline, to the first and second programming drivers thereof;
• (b) addressing, through the local bitlines and wordlines coupled to the first memory cells associated with the first programming driver, a direct memory cell or the respective complementary memory cell, establishing a conductive path between the first programming driver and the first memory cell addressed;
• (c) addressing, through the local bitlines and wordlines coupled to the second memory cells associated with the second programming driver, a direct memory cell or the respective complementary memory cell, establishing a conductive path between the second programming driver and the second memory cell addressed;
• and
• (d) supplying, through the first and second programming drivers, a first programming current, of a same type between SET and RESET currents, together with the first and second memory cells addressed in the steps (b) and (c);
• and
• in a second operating condition associated with a second time interval different from the first time interval:
• (e) for each between the first and second groups, activating the others between the direct selectors or the complementary selectors activated in the step (a), so as to electrically connect each direct, or, respectively, complementary main bitline, to the first and second programming drivers thereof;
• (f) addressing, through the local bitlines and wordlines coupled to the first memory cells associated with the first programming driver, the other direct or complementary memory cell with respect to that addressed in the step (b);
• (g) addressing, through the local bitlines and wordlines coupled to the second memory cells associated with the second programming driver, the other direct or complementary memory cell with respect to that addressed in the step (c);
• and
• (h) supplying, through the first and second programming drivers, a second programming current, of the other type between SET and RESET currents, together with the first and second memory cells addressed in the steps (f) and (g).