US 11,354,472 B2Granted

Automated circuit generation

AssigneeCelera Corporation

InventorsCalum MacRae, Jim LoCascio, Karen Mason, John Mason, Richard Philpott, Muhammed Abid Hussain

Life of this patent

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Abstract

Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

Claims19

Dependent claims

A computer-implemented method of generating a circuit comprising:

generating a circuit specification, said generating the circuit specification comprising:
receiving parameters specifying the circuit to be generated;
selecting, based on the parameters, predefined sub-circuit schematics to be included in the circuit;
determining, based on the parameters, connections between the predefined sub-circuit schematics;
generating the circuit specification for the circuit to be generated specifying the sub-circuit schematics and the connections between the predefined sub-circuit schematics;
and
generating a layout script associated with the circuit to be generated;
and
converting the circuit specification into a circuit schematic and a circuit layout, said converting comprising:
selecting predefined sub-circuit schematics specified in the circuit specification;
connecting the predefined sub-circuit schematics to form the circuit schematic;
converting the circuit schematic into a plurality of layout instances;
and
positioning the layout instances based on the layout script associated with the circuit to be generated to produce the circuit layout.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/886,577Filed 28 May 2020 · continuation
Priority: 30 May 2019
Published: US 2020/0380192 A13 Dec 2020
Granted: 7 Jun 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/31
Circuit design: design entry, e.g. editors specifically adapted for circuit design
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…

Family

Application62/854,848Us provisional application · filed 30 May 2019
Application16/882,217Parent of this continuation · filed 22 May 2020
US 2020/0380192 A1Pre-grant publication · published 3 Dec 2020
US 2020/0410153 A1Published application
US 11,354,472 B2This patent

From the US filing history. Foreign family members aren’t listed.