Circuits based on magnetoelectric transistor devices

A magneto-electric (ME) full adder comprising:

• a ME majority gate device coupled to receive a first input signal, a second input signal, and a third input signal and output a “carry” signal, wherein the ME majority gate device comprises a conducting device and a plurality of ME transistors, wherein at least one ME transistor of the plurality of ME transistors is coupled to the conducting device;
• and
• a stacked ME-XNOR device comprising a first ME-XNOR device and a second ME-XNOR device, wherein the first ME-XNOR device is coupled to receive the first input signal and second input signal and output an intermediate signal, and wherein the second ME-XNOR device is coupled to receive the third input signal and the intermediate signal and output a “sum” signal, wherein the first and second ME-XNOR devices each comprise:
• an associated ME transistor, wherein the associated ME transistor comprises:
• a split gate;
• a first gate terminal coupled to a first portion of the split gate for receiving a first particular input signal, the first particular input signal being the first input signal for the first ME-XNOR device and the third input signal for the second ME-XNOR device;
• a second gate terminal coupled to a second portion of the split gate for receiving a second particular input signal, the second particular input signal being the second input signal for the first ME-XNOR device and the intermediate signal for the second ME-XNOR device;
• a source terminal coupled to a ground line;
• and
• a drain terminal coupled to an associated conducting device.

A magneto-electric (ME) full adder comprising:

• a first ME majority gate device coupled to receive a first input signal, a second input signal, and a third input signal and output a “first carry” signal;
• a second ME majority gate device coupled to receive the first input signal, the second input signal, and a fourth input signal and output a “second carry” signal;
• a ME inverter device coupled to receive the “first carry” signal from the first ME majority gate device and output a “carry_bar” signal;
• and
• a third ME majority gate device coupled to receive the “carry_bar” signal from the ME inverter device, the third input signal, and the “second carry” signal from the second ME majority gate device and output a “sum” signal,
• wherein the first ME majority gate device comprises a first conducting device and a plurality of first ME transistors, wherein at least one first ME transistor of the plurality of first ME transistors is coupled to the first conducting device,
• wherein the second ME majority gate device comprises a second conducting device and a plurality of second ME transistors, wherein at least one second ME transistor of the plurality of second ME transistors is coupled to the second conducting device,
• wherein the ME inverter device comprises a conducting device and a ME transistor coupled to the conducting device, and
• wherein the third ME majority gate device comprises a third conducting device and a plurality of third ME transistors, wherein at least one third ME transistor of the plurality of third ME transistors is coupled to the third conducting device.