Transistor structure with a stress layer

A semiconductor structure for use in a III-Nitride (III-N) semiconductor device, comprising:

• a semiconductor layer comprising a first III-N material for providing electrical conduction;
• a barrier layer comprising a second III-N material;
• a source electrode and a drain electrode disposed in ohmic recesses in contact with the barrier layer;
• a trench region defined between the source electrode and the drain electrode, wherein trenches are etched into portions of the barrier layer between the source electrode and the drain electrode, wherein ridges are created between the trenches, wherein the ridges comprise the semiconductor layer and the barrier layer and extend from an area near the source electrode to an area near the drain electrode and traverse the trench region;
• a gate recess region defined in the trench region, wherein the gate recess region is narrower than the trench region such that the trenches are disposed on both sides of the gate recess region;
• a dielectric layer, wherein the dielectric layer fills at least a portion of the trenches and covers the barrier layer outside the gate recess region, and wherein a thickness of the dielectric layer in the gate recess region is less than in other areas;
• and
• a gate electrode disposed in the gate recess region, wherein the gate electrode is formed over the ridges.