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US 11,348,898 B2Granted
Systems and methods for releveled bump planes for chiplets
AssigneeXcelsis Corporation
InventorsJavier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
Life of this patent
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Abstract
An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
Claims17
A method for producing a chip configured to be stacked comprising:
- obtaining a chip configured to be stacked having a front surface and a back surface and a plurality of side surfaces;
- obtaining a plurality of chiplets configured to be bonded to the chip, at least one of the plurality of chiplets having a plurality of through silicon vias for interconnections between the chip and an external surface of the chiplet and having a front chiplet surface and a back chiplet surface and a plurality of side chiplet surfaces;
- bonding the chiplets to the chip such that a new outer surface is formed having multiple levels;
- forming a plurality of posts on the new outer surface, wherein at least some of the plurality of posts are formed on the chip and at least some of the plurality of posts are formed on one or more of the plurality of chiplets, wherein the plurality of posts terminate at a same level.
1 more element
Dependencies are inferred from the claim text.