Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations

A system, comprising:

• a scratchpad memory of a processing unit to provide an input vector having a width of X elements, where X is an integer;
• and
• a hardware accelerator coupled to the scratchpad memory of the processing unit, including compute near memory (CNM) circuitry having a multiply-accumulate (MAC) array, the MAC array including
• a local memory to store a weight matrix;
• and
• X MAC circuits to dynamically switch between a first configuration and a second configuration in response to a control signal,
• wherein in the first configuration, the X MAC circuits are to perform a matrix-matrix computation with the X elements of the input vector and a single element of the weight matrix;
• and
• wherein in the second configuration, the X MAC circuits are to perform a matrix-vector computation with a single element of the input vector and X elements of the weight matrix.